SMART 5 BOOT BLOCK MEMORY FAMILY
E
V
IH
RP# (P)
VCC
tPHQV
tPHWL
tPHEL
VIL
tPLPH
(A) Reset during Read Mode
R1
Abort
Complete
tPHQV
tPHWL
tPHEL
DEVICE
UNDER
OUT
t PLRH
TEST
VIH
VIL
CL
RP# (P)
R2
t PLPH
t PLPH
t PLRH
<
(B) Reset during Program or Block Erase,
Abort Deep
Complete Power-
0599-12
tPHQV
tPHWL
tPHEL
NOTE:
Down
t PLRH
CL includes jig capacitance.
VIH
VIL
RP# (P)
Figure 13. Test Configuration
t PLPH
Test Configuration Component Values
(C) Reset Program or Block Erase,
>
t PLPH tPLRH
0599-13
Test Configuration
5 V Standard Test
CL (pF) R1 (Ω) R2 (Ω)
Figure 14. AC Waveform for Reset Operation
Table 9. Reset Specifications(1)
100
30
580
580
390
390
5 V High-Speed Test
Sym
Parameter
Min Max Unit
tPLPH RP# Pulse Low
Time
60
ns
tPLRH RP# Low to Reset
during Prog/Erase
12
µs
1. If RP# is tied to V , these specs are not applicable.
CC
2. These specifications are valid for all product versions
(packages and speeds).
3. If RP# is asserted while a program or block erase, is
not executing, the reset will complete within tPLPH
.
4. A reset time, tPHQV, is required after tPLRH until outputs
are valid. See Section 3.1.5 for detailed information.
30
ADVANCE INFORMATION
INTEL [ INTEL ]
