欢迎访问ic37.com |
会员登录 免费注册
发布采购

E28F200B5B80 参数 Datasheet PDF下载

E28F200B5B80图片预览
型号: E28F200B5B80
PDF下载: 下载PDF文件 查看货源
内容描述: 智能5引导块闪存系列2 , 4 , 8兆比特 [SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 38 页 / 500 K
品牌: INTEL [ INTEL ]
 浏览型号E28F200B5B80的Datasheet PDF文件第29页浏览型号E28F200B5B80的Datasheet PDF文件第30页浏览型号E28F200B5B80的Datasheet PDF文件第31页浏览型号E28F200B5B80的Datasheet PDF文件第32页浏览型号E28F200B5B80的Datasheet PDF文件第34页浏览型号E28F200B5B80的Datasheet PDF文件第35页浏览型号E28F200B5B80的Datasheet PDF文件第36页浏览型号E28F200B5B80的Datasheet PDF文件第37页  
E
SMART 5 BOOT BLOCK MEMORY FAMILY  
5.7  
AC Characteristics—Write Operations—Commercial and Extended  
Temperature  
Comm  
Extended  
#
Sym  
Parameter  
Note Min Max Min Max Unit  
W1 tPHWL (tPHEL  
)
RP# High Recovery to WE# (CE#) Going  
Low  
450  
450  
ns  
W2 tELWL (tWLEL  
)
CE# (WE#) Setup to WE# (CE#) Going  
Low  
0
0
ns  
W3 tWP  
W4 tDVWH (tDVEH  
W5 tAVWH (tAVEH  
W6 tWHEH (tEHWH  
W7 tWHDX (tEHDX  
W8 tWHAX (tEHAX  
W9 tWPH  
Write Pulse Width  
9
4
3
50  
50  
50  
0
60  
60  
60  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
)
Data Setup to WE# (CE#) Going High  
Address Setup to WE# (CE#) Going High  
CE# (WE#) Hold from WE# (CE#) High  
Data Hold from WE# (CE#) High  
Address Hold from WE# (CE#) High  
Write Pulse Width High VCC = 5 V ± 5%  
)
)
)
4
3
0
0
)
0
0
10  
20  
10  
20  
VCC = 5 V ±  
10%  
W10 tPHHWH (tPHHEH  
)
RP# VHH Setup to WE# (CE#) Going High  
VPP Setup to WE# (CE#) Going High  
RP# VHH Hold from Valid SRD  
VPP Hold from Valid SRD  
6,8 100  
5,8 100  
100  
100  
0
ns  
W11 tVPWH (tVPEH  
)
ns  
ns  
W12 tQVPH  
W13 tQVVL  
6,8  
5,8  
7,8  
0
0
0
ns  
W14 tPHBR  
Boot Block Lock Delay  
100  
100 ns  
NOTES:  
1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer toAC  
Characteristics—Read-Only Operations.  
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally  
which includes verify operations.  
3. Refer to command definition table for valid A . (Table 6)  
IN  
4. Refer to command definition table for valid D . (Table 6)  
IN  
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).  
6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes  
successfully.  
7. Time tPHBR is required for successful locking of the boot block.  
8. Sampled, but not 100% tested.  
9. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last)to CE# or WE# going high  
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH  
.
10. Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first)to CE# or WE# going low  
(whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL  
.
33  
ADVANCE INFORMATION  
 复制成功!