Pentium® III Processor for the PGA370 Socket at 500 MHz to 866 MHz
Table 6. Voltage and Current Specifications 1, 2 (Sheet 2 of 2)
Symbol
Parameter
Core Freq
Min
Typ
Max
Unit
Notes
3, 8, 9
500E MHz
533EB MHz
550E MHz
600E MHz
600EB MHz
650 MHz
667B MHz
700 MHz
733B MHz
750 MHz
10.0
10.6
11.0
12.0
12.0
13.0
13.3
14.0
14.6
15.0
16.0
16.0
16.2
16.3
A
A
A
A
A
A
A
A
A
A
A
A
A
A
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
ICC
ICC for processor core
CORE
800 MHz
800EB MHz
850 MHz
866 MHz
ICC
ICC for Vcc
250
60
mA
µA
CMOS
CMOS
CLKREF voltage
supply current
ICLKREF
IVTT
Termination voltage
supply current
2.7
2.5
2.5
2.2
240
8
A
A
A
A
10
ICC Stop-Grant for
processor core
ISGnt
8, 11
8
ICC Sleep for processor
core
ISLP
ICC Deep Sleep for
processor core
IDSLP
Power supply current
slew rate
dICCCORE/dt
A/µs 12, 13, 14
Termination current
slew rate
12, 13, See
A/µs
dI TT/dt
v
Table 9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All specifications in this table apply only to the Pentium III processor. For motherboard compatibility with the
®
TM
®
TM
Intel Celeron processor, see the Intel Celeron Processor Datasheet.
3. Vcc and Icc supply the processor core and the on-die L2 cache.
CORE
CORE
4. Use the “typical voltage” specification with the “tolerance specifications” to provide correct voltage regulation
to the processor.
5. VTT and Vcc must be held to 1.5V ±9% while the AGTL+ bus is active. It is required that VTT and Vcc be
1.5
1.5
held to 1.5V ±3% while the processor system bus is static (idle condition). The ±3% range is the required
design target; ±9% will come from the transient noise added. This is measured at the PGA370 socket pins on
the bottom side of the baseboard.
6. These are the tolerance requirements, across a 20 MHz frequency bandwidth, measured at the
processor socket pin on the soldered-side of the motherboard. VCC
must return to within the static
CORE
voltage specification within 100 µs after a transient event; see the VRM 8.4 DC-DC Converter Design
Guidelines for further details.
7. V
should be generated from VTT by a voltage divider of 1% resistors or 1% matched resistors. Refer to the
REF
®
®
Intel Pentium II Processor Developer’s Manual for more details on V
.
REF
8. Maximum ICC is measured at VCC typical voltage and under a maximum signal loading conditions.
9. Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output
voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of Vcc
CORE
(Vcc
). In this case, the maximum current level for the regulator, Icc
, can be reduced from
CORE_TYP
CORE_REG
the specified maximum current Icc
and is calculated by the equation:
CORE _MAX
Icc
= Icc
× (Vcc
- Vcc
) / Vcc
CORE_STATIC_TOLERANCE CORE_TYP
CORE_REG
CORE_MAX
CORE_TYP
10.The current specified is the current required for a single processor. A similar amount of current is drawn
through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended termination is
used (see Section 2.1).
24
Datasheet
INTEL [ INTEL ]
