Pentium® III Processor for the PGA370 Socket at 500 MHz to 866 MHz
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available for
the Pentium III processor in the FC-PGA package in Viewlogic* XTK/XNS* model format
(formerly known as QUAD format) as the Pentium III Processor for the PGA370 Socket I/O Buffer
Models, XTK/XNS Format (Electronic Format).
AGTL+ layout guidelines are also available in the appropriate platform design guide.
Care should be taken to read all notes associated with a particular timing parameter.
2.13.1
I/O Buffer Model Password
An electronic copy of the I/O Buffer Model for the AGTL+ and CMOS signals is available at
Intel’s Developer’s Website (http://developer.intel.com). The model is for use in single processor
designs and assumes the presence of motherboard RTT values as described in Table 9 on page 26.
Table 10. System Bus AC Specifications (Clock)1, 2, 3
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
100.00
133.33
4
4
System Bus Frequency
MHz
10.0
7.5
4, 5, 10
4, 5, 11
T1: BCLK Period
ns
ps
ns
ns
7
±250
±250
6, 7, 10
6, 7, 11
T2: BCLK Period Stability
T3: BCLK High Time
T4: BCLK Low Time
2.5
1.4
9, 10
9, 11
7
7
2.4
1.4
9, 10
9, 11
T5: BCLK Rise Time
T6: BCLK Fall Time
0.4
0.4
1.6
1.6
ns
ns
7
7
8, 12
8, 12
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor pin.
All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00V at the processor pins.
3. N/A
4. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to
core clock ratio is determined during initialization. Individual processors will only operate at their specified
system bus frequency, either 100 MHz or 133 MHz, not both. Table 11 shows the supported ratios for each
processor.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the appropriate clock synthesizer/
driver specification for details.
6. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the rising edges of adjacent BCLKs crossing 1.25V at the processor pin. The jitter present
must be accounted for as a component of BCLK timing skew between devices.
7. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than 500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer. See the appropriate clock synthesizer/driver specification for details
8. BCLK Rise time is measure between 0.5V–2.0V. BCLK fall time is measured between 2.0V–0.5V.
9. BCLK high time is measured as the period of time above 2.0V. BCLK low time is measured as the period of
time below 0.5V
10.This specification applies to Pentium III processors operating at a system bus frequency of 100 MHz.
11.This specification applies to Pentium III processors operating at a system bus frequency of 133 MHz.
12.Not 100% tested. Specified by design characterization as a clock driver requirement.
Datasheet
27
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