Pentium® III Processor for the PGA370 Socket at 500 MHz to 866 MHz
2.8.2
System Bus Frequency Select Signals (BSEL[1:0])
These signals are used to select the system bus frequency. Table 2.9 defines the possible
combinations of the signals and the frequency associated with each combination. The frequency is
determined by the processor(s), chipset, and clock synthesizer. All system bus agents must operate
at the same frequency. The Pentium III processor for the PGA370 socket operates at 100 MHz
or 133 MHz system bus frequency; 66 MHz system bus operation is not supported. Individual
processors will only operate at their specified front side bus (FSB) frequency, either 100 MHz or
133 MHz, not both.
On motherboards that support operation at either 100 MHz or 133 MHz, the BSEL1 signal must be
pulled up to a logic high by a resistor located on the motherboard and provided as a frequency
selection signal to the clock driver/synthesizer. This signal can also be incorporated into RESET#
logic on the motherboard if only 133 MHz operation is supported (thus forcing the RESET# signal
to remain active as long as the BSEL1 signal is low.
The BSEL0 signal will float from the processor and should be pulled up to a logic high by a resistor
located on the motherboard. The BSEL0 signal can be incorporated into RESET# logic on the
motherboard if 66 MHz operation is unsupported, as demonstrated in Figure 6. Refer to the
appropriate clock synthesizer design guidelines and platform design guide for more details on the
bus frequency select signals.
In a 2-way MP system design, these BSEL[1:0] signals must connect the pins of both processors.
Figure 6. BSEL[1:0] Example for a 100/133 MHz or 100 MHz Only System Design
3.3V
3.3V
Processor
1
K
1 K
Ω
Ω
BSEL0
BSEL1
10
K
Ω
Note
1
Clock Driver
10
K
10
K
Ω
Ω
Note
2
Note
2
Chipset
NOTES:
1. Some clock drivers may require a series resistor on their BSEL1 input.
2. Some chipsets may connect to the BSEL[1:0] signals and require a series resistor. See the appropriate
platform design guide for implementation details.
Table 4. Frequency Select Truth Table for BSEL[1:0]
BSEL1
BSEL0
Frequency
0
0
1
1
0
1
0
1
66 MHz (unsupported)
100 MHz
Reserved
133 MHz
Datasheet
21
INTEL [ INTEL ]
