Pentium® III Processor for the PGA370 Socket at 500 MHz to 866 MHz
2.9
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the processor be the first in the TAP chain and followed by any other
components within the system. A translation buffer should be used to connect the rest of the chain
unless one of the other components is capable of accepting a 1.5V input. Similar considerations
must be made for TCK, TMS, and TRST# signals.
In a two-way MP system design, be cautious when including an empty PGA370 socket in the scan
chain. All sockets in the scan chain must have a processor installed to complete the chain or the
system must support a method to bypass the empty socket; PGA370 termination packages should
not connect TDI to TDO in order to avoid placing the TDO pull-up resistor in parallel.
2.10
Maximum Ratings
Table 5 contains processor stress ratings only. Functional operation at the absolute maximum and
minimum is not implied nor guaranteed. The processor should not receive a clock while subjected
to these conditions. Functional operating conditions are given in the AC and DC tables in
Section 2.11 through Section 2.13. Extended exposure to the maximum ratings may affect device
reliability. Furthermore, although the processor contains protective circuitry to resist damage from
static electric discharge, one should always take precautions to avoid high static voltages or electric
fields.
Table 5. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
TSTORAGE
Processor storage temperature
–40
85
°C
VCC
and
Processor core voltage and termination
supply voltage with respect to VSS
CORE
–0.5
2.1
V
VTT
Vin
Vin
AGTL+ buffer input voltage
VTT - 2.18
VTT - 2.18
2.18
2.18
V
V
1, 2
AGTL
CMOS buffer DC input voltage with respect
to VSS
1.5
1, 2, 3
CMOS
CMOS buffer DC input voltage with respect
to VSS
Vin
2.5
-0.58
3.18
V
4
CMOS
IVID
Max VID pin current
5
5
mA
mA
ICPUPRES#
Max CPUPRES# pin current
NOTES:
1. Input voltage can never exceed VSS + 2.18 volts.
2. Input voltage can never go below VTT - 2.18 volts.
3. Parameter applies to CMOS (except BCLK, PICCLK, and PWRGOOD), APIC, and TAP bus signal groups
only.
4. Parameter applies to CMOS signals BCLK, PICCLK, and PWRGOOD only.
22
Datasheet
INTEL [ INTEL ]
