Pentium® III Processor for the PGA370 Socket at 500 MHz to 866 MHz
Table 11. Valid System Bus to Core Frequency Ratios 1, 2, 3
Core Frequency
(MHz)
BCLK Frequency
(MHz)
Frequency
Multiplier
Processor
L2 Cache (MHz)
500E
533EB
550E
600E
600EB
650
500
533
100
133
5
4
500
533
550
100
11/2
6
550
600
100
600
600
133
9/2
13/2
5
600
650
100
650
667B
700
667
133
667
700
100
7
700
733B
750
733
133
11/2
15/2
8
733
750
100
750
800
800.00
800.00
850.00
866.00
100.00
133.33
100.00
133.33
800.00
800.00
850.00
866.00
800EB
850
6
17/2
13/2
866
NOTE:
1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency
multipliers.
2. While other bus ratios are defined, operation at frequencies other than those listed are not supported by the
Pentium III processor.
3. Individual processors will only operate at their specified system bus frequency. Either 100 MHz or 133 MHz,
not both.
Table 12. System Bus AC Specifications (AGTL+ Signal Group)1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
4, 10, 11
T7: AGTL+ Output Valid Delay
0.40
3.25
ns
8
T8: AGTL+ Input Setup Time
BREQ lines
1.20
0.95
ns
ns
9
9
5, 6, 7, 10
133 MHz
5, 6, 7, 11, 12
T9: AGTL+ Input Hold Time
T10: RESET# Pulse Width
1.00
1.00
ns
9
8, 10
ms
10
6, 9, 10
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor pin.
All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00V at the processor pins.
4. Valid delay timings for these signals are specified into 50 Ω to 1.5V, V
at 1.0 V ±2% and with 56 Ω on-die
REF
R
.
TT
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. For 2-way MP
systems, RESET# should be synchrounous.
7. Specification is for a minimum 0.40 V swing from V
rate of 0.3V/ns.
- 200 mV to V
+ 200 mV. This assumes an edge
REF
REF
8. Specification is for a maximum 1.0 V swing from VTT - 1V to VTT. This assumes an edge rate of 3V/ns.
9. This should be measured after VCC , VTT, Vcc , and BCLK become stable.
CORE
CMOS
10.This specification applies to the Pentium III processor running at 100 MHz system bus frequency.
11.This specification applies to the Pentium III processor running at 133 MHz system bus frequency.
12.BREQ signals at 133 MHz system bus observe a 1.2 ns minimum setup time.
28
Datasheet
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