Pentium® III Processor for the PGA370 Socket at 500 MHz to 866 MHz
Table 3. System Bus Signal Groups 1
Group Name
Signals
7
6
AGTL+ Input
BPRI#, BR1# , DEFER#, RESET# , RS[2:0]#, RSP#, TRDY#
PRDY#
AGTL+ Output
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0# , D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#
AGTL+ I/O
2
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#,
STPCLK#
3
CMOS Input
4
CMOS Input
PWRGOOD
3
CMOS Output
FERR#, IERR#, THERMTRIP#
System Bus
Clock
BCLK
4
4
APIC Clock
PICCLK
3
APIC I/O
PICD[1:0]
3
TAP Input
TCK, TDI, TMS, TRST#
TDO
3
TAP Output
BSEL[1:0], CLKREF, CPUPRES#, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL,
5
8
Power/Other
THERMDN, THERMDP, RTTCTRL , VCORE
, VID[3:0], VCC , VCC , VCC ,
DET 1.5 2.5 CMOS
VCC
, V
, VSS, VTT, Reserved
CORE
REF
NOTES:
1. See Section 7.0 for information on the these signals.
2. The BR0# pin is the only BREQ# signal that is bidirectional. See Section 7.0 for more information. The
internal BREQ# signals are mapped onto the BR[1:0]# pins after the agent ID is determined.
3. These signals are specified for Vcc
4. These signals are 2.5 V tolerant.
(1.5 V for the Pentium III processor) operation.
CMOS
5. VCC
is the power supply for the processor core and is described in Section 2.6.
CORE
VID[3:0] is described in Section 2.6.
VTT is used to terminate the system bus and generate V
VSS is system ground.
on the motherboard.
REF
VCC , VCC , Vcc
are described in Section 2.3.
1.5 2.5 CMOS
BSEL[1:0] is described in Section 2.8.2 and Section 7.0.
All other signals are described in Section 7.0.
6. RESET# must always be terminated to VTT on the motherboard, on-die termination is not provided for this
signal.
®
7. This signal is not supported by all processors. Refer to the Pentium III Processor Specification Update for a
complete listing of processors that support this pin.
8. This signal is used to control the value of the processor on-die termination resistance. Refer to the platform
design guide for the recommended pulldown resistor value.
2.8.1
Asynchronous vs. Synchronous for System Bus Signals
All AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signals
can be applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK. All TAP
signals are synchronous to TCK.
20
Datasheet
INTEL [ INTEL ]
