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80502500E256 参数 Datasheet PDF下载

80502500E256图片预览
型号: 80502500E256
PDF下载: 下载PDF文件 查看货源
内容描述: [Microprocessor, 64-Bit, 500MHz, CMOS, CPGA370, PGA-370]
分类和应用: 时钟外围集成电路
文件页数/大小: 76 页 / 564 K
品牌: INTEL [ INTEL ]
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Pentium® III Processor for the PGA370 Socket at 500 MHz to 866 MHz  
2.5  
Processor System Bus Clock and Processor Clocking  
The BCLK input directly controls the operating speed of the system bus interface. All AGTL+  
system bus timing parameters are specified with respect to the rising edge of the BCLK input. See  
the P6 Family of Processors Hardware Developer's Manual for further details.  
2.5.1  
Mixing Processors of Differrent Frequencies  
In two-way MP (multi-processor) systems, mixing processors of different internal clock  
frequencies is not supported and has not been validated. Pentium III processors do not support a  
variable multiplier ratio; therefore, adjusting the ratio setting to a common clock frequency is not  
valid. However, mixing processors of the same frequency but of different steppings is supported.  
Details on support for mixed steppings is provided in the Pentium® III Processor Specification  
Update.  
Note: Not all Pentium III processors for the PGA370 socket are validated for use in dual processor (DP)  
systems. Refer to the Pentium® III Processor Specification Update to determine which processors  
are DP capable.  
2.6  
Voltage Identification  
There are four voltage identification pins on the PGA370 socket. These pins can be used to support  
automatic selection of VCCCORE voltages. These pins are not signals, but are either an open circuit  
or a short circuit to VSS on the processor. The combination of opens and shorts defines the voltage  
required by the processor core. The VID pins are needed to cleanly support voltage specification  
variations on current and future processors. VID[3:0] are defined in Table 2. A 1in this table  
refers to an open pin and a 0refers to a short to ground. The voltage regulator or VRM must  
supply the voltage that is requested or disable itself.  
To ensure a system is ready for current and future processors, the range of values in bold in Table 2  
should be supported. A smaller range will risk the ability of the system to migrate to a higher  
performance processor and/or maintain compatibility with current processors.  
Datasheet  
17  
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