Pentium® III Processor for the PGA370 Socket at 500 MHz to 866 MHz
Figure 5. Processor VCCCMOS Package Routing
2.5V
2.5V Supply
VCC CMOS
Intel®
Pentium® III
Processor
0.1 uF
1.5V
1.5V Supply
CMOS Signals
CMOS
Pullups
*ICH or
Other Logic
Note: *Ensure this logic is compatible
with 1.5V signal levels of the
Intel® Pentium® III processor
for the PGA370 socket.
2.3.1
Phase Lock Loop (PLL) Power
It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements.
A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,
decoupled power source for the internal PLL. Please refer to the Phase Lock Loop Power section in
the appropriate platform design guide for the recommended filter specifications.
2.4
Decoupling Guidelines
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. The fluctuations can
cause voltages on power planes to sag below their nominal values if bulk decoupling is not
adequate. Care must be taken in the board design to ensure that the voltage provided to the
processor remains within the specifications listed in Table 6. Failure to do so can result in timing
violations (in the event of a voltage sag) or a reduced lifetime of the component (in the event of a
voltage overshoot). Unlike SC242 based designs, motherboards utilizing the PGA370 socket
must provide high frequency decoupling capacitors on all power planes for the processor.
2.4.1
2.4.2
Processor VCCCORE Decoupling
The regulator for the VCCCORE input must be capable of delivering the dICCCORE/dt (defined in
Table 6) while maintaining the required tolerances (also defined in Table 6). Failure to meet these
specifications can result in timing violations (during VCCCORE sag) or a reduced lifetime of the
component (during VCCCORE overshoot).
Processor System Bus AGTL+ Decoupling
The processor requires both high frequency and bulk decoupling on the system motherboard for
proper AGTL+ bus operation. See the AGTL+ buffer specification in the Intel® Pentium® II
Processor Developer's Manual for more information. Also, refer to the appropriate platform design
guide for recommended capacitor component placement.
16
Datasheet
INTEL [ INTEL ]
