Signal Description
2.16.1.2
PCI Message Signaled Interrupts (MSI)
These interrupts which appear on the PCI bus as inbound memory writes are decoded by the
Intel® 6702PXH 64-bit PCI Hub in the PCI bridge inverse decode window and passed upstream
without any modifications. BIOS would setup the PCI bridge decode register such that
0xFEEx_xxxx falls in the inverse decode window of the Intel® 6702PXH 64-bit PCI Hub.
2.16.2
PCI Express Legacy INTx Support and Boot Interrupt
The Intel® 6702PXH 64-bit PCI Hub has the capability to generate an in-band interrupt request on
the PCI Express bus when the APIC is disabled. This in-band interrupt mechanism is necessary for
systems that do not support the APIC and for boot. The PCI Express protocol describes an in-band
legacy wire-interrupt INTx mechanism for I/O devices to signal PCI-style level interrupts. The
Intel® 6702PXH 64-bit PCI Hub generates a PCI Express INTx message as follows: each interrupt
pin input (16 interrupt pins) and INT[23]# is compared with its mask (bit 16 in the redirection table
low, RDL register). If the interrupt is masked in the Intel® 6702PXH 64-bit PCI Hub APIC, that
interrupt needs to cause an INTx message over the PCI Express bus whenever asserted. If the
interrupt is not masked, then that interrupt is being used by the Intel® 6702PXH 64-bit PCI Hub
APIC and should not cause an INTx message on the PCI Express bus.
In the PCI Express protocol, boot interrupts are virtualized using a pair of ASSERT and
DEASSERT messages. This then gives a way to preserve the level-sensitive semantics of the PCI
interrupts on the PCI Express bus. The ASSERT message will capture the asserting edge of the
signal that represents the logical OR of all of the Intel® 6702PXH 64-bit PCI Hub’s interrupt pins.
The logical OR’ing includes both PCI sides A and B for the Intel® 6702PXH 64-bit PCI Hub. The
DEASSERT message captures the deasserting edge of the signal that represents the logical OR of
all of the Intel® 6702PXH 64-bit PCI Hub’s interrupt pins.
Table 2-30. Intel® 6702PXH 64-bit PCI Hub INTx Routing
PCI Interrupt Pins
Internal Interrupts
PCI Express* INTx Message
0, 4, 8, 12
1, 5, 9, 13
2, 6, 10, 14
3, 7, 11, 15
SHPC A (IRQ[23])
INTA
INTB
INTC
INTD
SHPC B
-
-
2.16.3
2.16.4
Buffer Flushing
The Intel® 6702PXH 64-bit PCI Hub does not implement any buffer flushing features. When the
Intel® 6702PXH 64-bit PCI Hub receives an interrupt on its interrupt pin, it does not flush its
posted write buffers in the inbound direction in the PCI interface. This is not required from the
Intel® 6702PXH 64-bit PCI Hub because PCI device drivers ultimately have to guarantee that all
posted writes from the device to the memory are all flushed before executing the interrupt service
routine.
EOI Special Cycles
The Intel® 6702PXH 64-bit PCI Hub can receive EOI special cycles over PCI Express in the IA-32
processor system bus mode. This is the result of the MCH broadcasting the IA-32 processor system
bus EOI cycle. Both I/OxAPICs in the Intel® 6702PXH 64-bit PCI Hub would compare the vector
Intel® 6702PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
