Signal Description
for the configuration access. Each of the parameters above is sent on SMBus in separate bytes. The
register number parameter is initialized with two bytes and Intel® 6702PXH 64-bit PCI Hub
ignores the most significant 4 bits of the second byte that initializes the register number. For
memory reads and writes, the write sequence initializes the:
• Destination memory
• 24-bit memory address offset (in 3 separate bytes on SMBus)
The destination memory is a byte of information that indicates the internal memory space to access
in the Intel® 6702PXH 64-bit PCI Hub. The 24-bit address offset is used to address any internal
memory with up to an offset of 24 bits. The Intel® 6702PXH 64-bit PCI Hub only uses 12 bits of
address, and ignores the most significant 12 bits of the 24-bit address. The Intel® 6702PXH 64-bit
PCI Hub slave interface always expects 24 bits of address from the SMBus master though it uses
only 12 bits.
The initialization of the information can be accomplished through any combination of the
supported SMBus write commands (Block, Word or Byte). The Internal Command field for each
write should specify the same internal command every time (read or write). After all the
information is set up, the last write (End bit is set) initiates an internal read or write command. On
an internal read if the data is not available before the slave interface acknowledges this last write
command (ACK), the slave will “clock stretch” until the data returns to the SMBus interface unit.
On a internal write, if the write is not complete before the slave interface acknowledges this last
write command (ACK), the salve will “clock stretch” until the write completes internally. If an
error occurs (internal timeout, target or master abort on the internal switch) during the internal
access, the last write command will receive a NACK.
2.17.3
Configuration And Memory Reads
Intel® 6702PXH 64-bit PCI Hub supports only read dword to internal register space. All
Configuration and memory reads are accomplished through an SMBus write(s) and later followed
by an SMBus read to read the status and the read data. For SMBus read transactions, the last byte
of data (or the PEC byte if enabled) is NACK’d by the master to indicate the end of the transaction.
The SMBus memory read command returns the status of the previous internal command and the
data associated previous internal read command. The status field encoding is shown in Table 2-35.
Table 2-35. SMBus Status Byte Encoding
Bit
Description
7
6
Internal Timeout: This bit is set if an SMBus request is not completed in 2 ms internally.
Reserved.
5
Internal Master Abort.
Internal Target Abort.
Reserved
4
3:1
0
Successful.
Examples of configuration and memory reads are shown in Figure 2-1 to Figure 2-6. For the
definition of the diagram conventions below, refer to the SMBus Specification, Revision 2.0.
Intel® 6702PXH 64-bit PCI Hub Datasheet
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