Signal Description
2.15.1.2
Outbound Transaction Ordering
Table 2-29 lists the combined set of ordering rules in the outbound path of the Intel® 6702PXH
64-bit PCI Hub.
Table 2-29. Outbound Transaction Ordering
Delayed (Split) Delayed (Split)
Delayed (Split)
Read Request
Row pass Column
Posted Write
Read
Write
Completion
Completion
Posted Write
No
No
No
Yes
Yes1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Delayed/Split Read Request
Delayed/Split
Write Request
Delayed/Split IO Write Completion
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Delayed/Split
Read Completion
NOTE: The Intel® 6702PXH 64-bit PCI Hub supports two outbound completion required requests per PCI
segment. Outbound delayed/split read requests can pass each other when issued on the PCI bus.
2.16
I/OxAPIC Interrupt Controller (Functions 1)
The Intel® 6702PXH 64-bit PCI Hub contains one I/OxAPIC controller, which reside on the
primary bus. The intended use of the controller on the Intel® 6702PXH 64-bit PCI Hub is to have
the interrupts from PCI bus A connected to the interrupt controller on function 1.
2.16.1
Interrupt Support
The Intel® 6702PXH 64-bit PCI Hub behaves as a normal peer-to-peer bridge and can handle PCI
IRQ# and PCI MSI system interrupt mechanisms.
2.16.1.1
PCI IRQ# Interrupts
The Intel® 6702PXH 64-bit PCI Hub can manage 16 pin interrupts, and has 16 pins (PAIRQ#) for
these interrupts. Interrupts delivered by a pin can be either in level or edge mode, and may be either
active high or active low. Since this I/OxAPIC is connected to a PCI bus, its most likely
configuration will be as active low level, which will match the PCI pin polarity and functionality.
Each pin is collected by the Intel® 6702PXH 64-bit PCI Hub, synchronized into the PCI clock
domain, and scheduled for delivery if it is unmasked.
The Intel® 6702PXH 64-bit PCI Hub only has 16 interrupt pins per PCI segment. These pins are
connected to I/OxAPIC redirection table entries 15 – 0 (of 24 entries). The standard hot plug
controller is hard-wired to redirection table entry 23 of the I/OxAPIC. All other interrupts are only
addressable through the PCI virtual wire mechanism. If PAIRQ[12:11]# are unused, they must be
pulled up to VCC33 to ensure the boot interrupt works correctly. All other IRQ pins are terminated
on-die.
58
Intel® 6702PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
