Signal Description
Table 2-32. System Bus Delivery Data Format (Sheet 2 of 2)
Bit
Description
10:8
Delivery Mode: This is the same as the corresponding bits in the I/O Redirection Table for that
interrupt.
7:0
Vector: This is the same as the corresponding bits in the I/O Redirection Table for that interrupt.
2.17
SMBus Interface
The SMBus address is set upon PWROK by sampling SMBUS[5] and SMBUS[3:1]. When the
pins are sampled, the resulting Intel® 6702PXH 64-bit PCI Hub SMBus address is shown in
Table 2-33.
Table 2-33. SMBus Address Configuration
Bit
Value
7
6
5
4
3
2
1
1
1
SMBUS[5]
0
SMBUS[3]
SMBUS[2]
SMBUS[1]
The SMBus controller has access to all internal registers in the Intel® 6702PXH 64-bit PCI Hub. It
can perform reads and writes from all registers through the particular interface’s configuration or
memory space. I/OxAPIC memory space is accessible through its configuration space. SHPC
memory space is directly accessible from the SMBus controller via the SMBus memory command.
2.17.1
SMBus Commands
The Intel® 6702PXH 64-bit PCI Hub supports six SMBus commands:
• Block Write
• Block Read
• Word Write
• Word Read
• Byte Write
• Byte Read
Sequencing these commands will initiate internal accesses to Intel® 6702PXH 64-bit PCI Hub’s
configuration and memory registers. For high reliability, Intel® 6702PXH 64-bit PCI Hub also
supports the optional Packet Error Checking feature (CRC-8) and is enabled or disabled with each
transaction.
Intel® 6702PXH 64-bit PCI Hub Datasheet
61
INTEL [ INTEL ]
