Signal Description
2.14.2.1.17 Prefetchable Memory Base and Limit Address Registers, Upper 32-bit
Registers
The prefetchable memory base and address registers, along with their upper 32-bit counterparts,
define an additional address range that the Intel® 6702PXH 64-bit PCI Hub uses to forward
accesses. The Intel® 6702PXH 64-bit PCI Hub forwards a memory transaction from the PCI
Express interface to PCI if the address falls within the range, and forwards transactions from PCI to
the PCI Express interface (or the peer bridge) if the address is outside the range and do not fall into
the regular memory range. This memory range supports 64-bit addressing, and supports 1-Mbyte
granularity and alignment.
This lower 32-bits of the range are defined by a 16-bit base register at offset 24h in configuration
space and a 16-bit limit register at offset 28h. The top 12 bits of each of these registers correspond
to bits [31:20] of the memory address. The low 4 bits are hardwired to VCC, indicating 64-bit
address support. The low 20 bits of the base address are assumed to be all 0s, which results in a
natural alignment to a 1-Mbyte boundary. The low 20 bits of the limit address are assumed to be all
1s, which results in an alignment to the top of a 1-Mbyte block.
The upper 32-bits of the range are defined by a 32-bit base register at offset 28h in configuration
space, and a 32-bit limit register at offset 2Ch.
Note: Setting the entire base (with upper 32-bits) to a value greater than that of the limit turns off the
memory range.
2.14.2.1.18 Memory Accesses to I/OxAPIC and SHPC Memory Space
Memory accesses to I/OxAPIC memory space are handled through two address ranges and an
access enable bit in I/OxAPIC configuration space, as follows:
• A 32-bit BAR (MBAR)
• An alternate 32-bit BAR (ABAR)
• Memory space enable bit (MSE) in the Command register
Refer to the chapter on I/OxAPIC for more details about these BARs. Memory accesses to SHPC
memory space are handled through a 64-bit and an access enable bit:
• A 64-bit BAR (SHPC_BAR)
• Memory space enable bit (MSE) in the Command register
2.14.3
VGA Addressing
2.14.3.1
Mode Access Mechanism
When a VGA-compatible device exists behind a Intel® 6702PXH 64-bit PCI Hub bridge, the VGA
Enable bit (bit 3) in the Bridge Control Register must be set (offset 3E–3Fh). If this bit is set, the
Intel® 6702PXH 64-bit PCI Hub forwards all transactions addressing the VGA frame buffer
memory and VGA I/O registers from the PCI Express interface to PCI, regardless of the values of
the Intel® 6702PXH 64-bit PCI Hub base and limit address registers. The Intel® 6702PXH 64-bit
PCI Hub will not forward VGA frame buffer memory accesses to the PCI Express interface
regardless of the values of the memory address ranges. However, the I/O Enable and Memory
Enable bits in the PD_CMD Register must still be set. When the bit is cleared, the Intel® 6702PXH
64-bit PCI Hub forwards transactions addressing the VGA frame buffer memory and VGA I/O
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Intel® 6702PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
