Signal Description
registers from PCI Express to PCI if the defined memory address ranges enable forwarding. All
accesses to the VGA frame buffer memory are forwarded from the PCI bus to the PCI Express
interface if the defined memory address ranges enable forwarding. However, the master enable bit
must still be set. The VGA I/O addresses are never forwarded to the PCI Express interface.
The VGA frame buffer consists of the following memory address range: 000A 0000h–00B FFFFh
The VGA I/O addresses consist of the I/O addresses 3B0h–3BBh and 3C0h–3DFh. These I/O
addresses are aliased every 1 Kbyte throughout the first 64 Kbytes of I/O space. This means that
address bits [9:0] (3B0h–3BBh and 3C0h–3DFh) are decoded, [15:10] are not decoded and can be
any value, and address bits [31:16] must be all 0s.
2.15
Transaction Ordering
2.15.1
Intel® 6702PXH 64-bit PCI Hub Transaction Ordering
The Intel® 6702PXH 64-bit PCI Hub follows the producer-consumer model of a standard PCI
Express-PCI bridge. Based on this model, the Intel® 6702PXH 64-bit PCI Hub implements a set of
ordering rules in the inbound and outbound directions. The ordering plane covered by these rules
spans the transaction domain covered by PCI Express. The Intel® 6702PXH 64-bit PCI Hub uses a
single PCI Express virtual channel to communicate with the MCH.
Accesses to the internal Intel® 6702PXH 64-bit PCI Hub configuration registers, which includes
the bridge configuration registers and the CSR memory registers, follow no ordering relationship
with respect to transactions moving to and from the PCI and PCI Express buses. Outbound
memory/configuration transactions to the internal register space could complete out of order with
respect to transactions pending in the outbound queues towards the PCI bus. Software must be
aware that any semaphore mechanism implemented through the internal Intel® 6702PXH 64-bit
PCI Hub register space requires a dummy read to PCI or PCI Express space to push the writes that
could be pending in the Intel® 6702PXH 64-bit PCI Hub queues in either direction. The ordering
tables in the next two sections do not consider these transactions.
2.15.1.1
Inbound Transaction Ordering
Table 2-28 lists the combined set of ordering rules in the inbound path of the Intel® 6702PXH
64-bit PCI Hub.
Table 2-28. Inbound Transaction Ordering
Delayed/Split
Read
Completion
Delayed/Split
Write
Completion
Delayed/Split
Read Request
Row pass Column
Posted Write
Posted Write
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
No
No
No
No
Delayed/Split Read Request
Delayed/Split IO Write Request
Delayed/Split Read Completion
Delayed/Split
Write Completion
Intel® 6702PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
