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6702PXH 参数 Datasheet PDF下载

6702PXH图片预览
型号: 6702PXH
PDF下载: 下载PDF文件 查看货源
内容描述: 64位PCI中枢 [64-bit PCI Hub]
分类和应用: PC
文件页数/大小: 214 页 / 2554 K
品牌: INTEL [ INTEL ]
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Signal Description  
Every configuration and memory read or write first consists of an SMBus write sequence which  
initializes the Bus Number, Device, function number, memory address offset etc. The term  
sequence is used since these variables can be initialized by the SMBus master with a single block  
write or multiple word or byte writes. The last write in the sequence that completes the  
initialization performs the internal configuration/memory read or write. The SMBus master can  
then initiate a read sequence which returns the status of the internal read or write command and  
also the data in case of a read.  
Each SMBus transaction has an 8-bit command driven by the master. The command encodes  
information as shown in Table 2-34.  
Table 2-34. SMBus Command Encoding  
Bit  
Description  
7
6
5
Begin: When set, this bit indicates the first transaction of the read or write sequence.  
End: When set, this bit indicates the last transaction of the read or write sequence.  
Memory/Configuration: This bit indicates whether memory or configuration space is being accessed in  
this SMBus sequence.  
1 = Memory Space  
0 = Configuration Space  
4
PEC Enable: When set, indicates PEC is enabled for the sequence. When enabled, each transaction in  
the sequence ends with an extra CRC byte. The Intel® 6702PXH 64-bit PCI Hub checks for CRC bytes  
on writes and generates CRC on reads.  
3:2 Internal Command:  
00 = Read DWord  
01 = Write Byte  
10 = Write Word  
11 = Write DWord  
All accesses are naturally aligned to the access width. This field specifies the internal command to be  
issued by the SMBus slave logic to the Intel® 6702PXH 64-bit PCI Hub core.  
1:0 SMBus Command:  
00 = Byte  
01 = Word  
10 = Block  
11 = Reserved  
This field indicates the SMBus command to be issued on the SMBus interface. It is used as an indication  
of the length of the transfer so that the slave knows when to expect the PEC packet (if enabled).  
2.17.2  
Initialization Sequence  
All Configuration and memory read and writes are accomplished through SMBus write(s) and later  
followed by an SMBus read (for a read command). The SMBus write sequence is used to initialize  
the:  
Bus Number,  
Device/Function and  
12-bit Register Number (in 2 separate bytes on SMBus)  
62  
Intel® 6702PXH 64-bit PCI Hub Datasheet