Register Description
Table 3-1. Configuration Register Summary (Sheet 2 of 4)
Address
Offset
Symbol
Register Name
Default
Access
1E–1Fh
20–21h
22–23h
24–25h
26–27h
28–2Bh
SECSTS
Secondary Status Register
Memory Base Register
02A0h
0000h
0000h
0001h
0001h
RWC,RO
RW
MB
ML
Memory Limit Register
RW
PMB
Prefetchable Memory Base Register
Prefetchable Memory Limit Register
RW, RO
RW, RO
RW
PML
PB_UPPER
Prefetchable Base Upper 32 Bits
Register
00000000h
2C–2Fh
PL_UPPER
Prefetchable Limit Upper 32 Bits
Register
00000000h
RW
30–31h
32–33h
34h
IOLU16
IOBU16
CAPP
I/O Limit Upper 16 Bits Register
I/O Base Upper 16 Bits Register
Capabilities Pointer Register
0000h
0000h
44h
RO
RO
RO
RW
3Ch
INTRL
Interrupt Line Information Register
0100h (Fn 0)
0200h (Fn 2)
3Dh
INTRP
Interrupt Pin Information Register
Bridge Control Register
0100h (Fn 0)
0200h (Fn 2)
RO
3E–3Fh
40–41h
BRIDGE_CNT
CNF
0000h
RW,
RWC, RO
Intel® 6700PXH 64-bit PCI Hub
Configuration Register
0080h
RW,
RWS, RO
42h
43h
44h
MTT
Multi-Transaction Timer Register
PCI Clock Control Register
00h
FFh
01h
RW, RO
RW, RO
RO
PCLKC
EXP_CAPID
PCI Express* Capability Identifier
Register
45h
EXP_NXTP
PCI Express* Next Item Pointer
Register
5Ch
RO
46–47h
48–4Bh
EXP_CAP
PCI Express* Capability Register
0030h
RO
RO
EXP_DEVCAP
PCI Express* Device Capabilities
Register
00000001h
4C–4Dh
EXP_DEVCNTL
PCI Express* Link Device Control
Register
0000h
RW, RO
4E–4Fh
50–53h
EXP_DSTS
EXP_LCAP
PCI Express* Device Status Register 0000h
RWC, RO
RO
PCI Express* Link Capabilities
Register
000B0211h
54–55h
56–57h
EXP_LCNTL
EXP_LSTS
PCI Express* Link Control Register
PCI Express* Link Status Register
0000h
RW, RO
RO
0000h (X1)
0040h (X4)
0080h (X8)
5Ch
5Dh
MSI_CAPID
MSI_NXTP
PCI Express* MSI Capability
Identifier Register
05h
RO
RO
PCI Express* MSI Next Item Pointer
Register
6Ch
82
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
