Register Description
Symbol
Description
Default Value Upon a Full Reset, the Intel® 6700PXH 64-bit PCI Hub sets its internal configuration registers
Upon Reset
to predetermined default states. The default state represents the minimum functionality
feature set required to successfully bring up the system. Hence, it does not represent the
optimal system configuration. It is the responsibility of the system initialization software
(usually BIOS) to properly determine the operating parameters and optional system features
that are applicable, and to program the Intel® 6700PXH 64-bit PCI Hub registers accordingly.
3.5
PCI Express*-to-PCI Bridges (D0:F0, F2)
3.5.1
Configuration Registers
The bridge configuration space follows the standard PCI-to-PCI bridge configuration space format.
Table 3-1 shows the Intel® 6700PXH 64-bit PCI Hub configuration registers and their address byte
offset values.
Note: Registers that are not shown should be treated as Reserved.
Table 3-1. Configuration Register Summary (Sheet 1 of 4)
Address
Offset
Symbol
Register Name
Default
8086h
Access
RO
00–01h
VID
DID
Vendor ID Register
02–03h
Device ID Register
Intel® 6700PXH
64-bit PCI Hub:
RO
•
•
0329h (Fn 0)
032Ah (Fn 2)
Intel® 6702PXH
64-bit PCI Hub:
•
032Ch (Fn 0)
04–05h
06–07h
08h
CMD
STS
Command Register
0000h
0010h
00h
RW, RO
RWC, RO
RO
Status Register
REVID
CC
Revision ID Register
09–0Bh
0Ch
Class Code Register
060400h
00h
RO
CLS
Cache Line Size Register
Master Latency Timer Register
Header Type Register
RW
0Dh
MLT
00h
RW
0Eh
HEADTYP
SHPC_BAR
PBN
81h
RO
10–17h
18h
SHPC Base Address Register
Primary Bus Number Register
Secondary Bus Number Register
Subordinate Bus Number Register
Secondary Latency Timer Register
00000008h
00h
RW, RO
RW
19h
SCBN
SBBN
SLT
00h
RW
1Ah
00h
RW
1Bh
00h (PCI)
RW
40h (PCI-X)
1Ch
1Dh
IOB
IOL
I/O Base Register
I/O Limit Register
00h
00h
RW, RO
RW, RO
Intel® 6700PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
