Register Description
Bits
1:0
Type
Reset
Description
RO
x
Slot State (SLOT_STATUS): This field reports the current state of the slot.
00b Reserved
01b Powered Only
10b Enabled
11b Disabled
3.7.2.2
SEVL – Slot Event Latch Field, Bits [23:16]
The Slot Event Latch field reports all latched events detected by the SHPC.
Bits
Type
Reset
Description
23:21
20
RO
0
0
Reserved.
RWC
Connected Power Fault Detected (CPFD): This bit is set when a connected
power fault is detected by the power control circuitry for this slot.
19
18
RWC
RWC
0
0
MRL Sensor Change Detected (MRLSCD): This bit is set when the MRL
Sensor bit in the Slot Status field changes state indicating a change in the
position of the MRL.
Attention Button Press Detected (ABPD): This bit is set when the Attention
Button bit in the Slot Status field transitions from 0 to 1 indicating the Attention
Button has been pressed.
17
16
RWC
RWC
0
0
Isolated Power Fault Detected (IPFD): This bit is set when an isolated power
fault is detected by the power control circuitry for this slot.
Card Presence Change Detected (CPCD): This bit is set when a change is
detected on the PRSNT1#/PRSNT2# bits defined in the Slot Status field.
3.7.2.3
SSIM – Slot SERR-INT Mask Field, Bits [31:24]
The Slot SERR-INT Mask field controls masking and unmasking of system interrupts and system
errors generated from events detected by the SHPC.
Bits
Type
Reset
Description
31
30
RO
0
1
Reserved.
RW
Connected Power Fault SERR Mask (CPFSM): If this bit is set, SERR
assertions from Connected Power Fault Detected are masked. The state of
this bit has no effect on the state of the Connected Power Fault Detected bit.
When this bit is clear, then connected power faults can cause ERR_FATAL
message on the PCI Express* bus provided the SERR enable bit in the
PCICMD register is set or the ERR_FATAL enable bit is set in the PCI
Express* capability.
29
28
RW
RW
1
1
MRL Sensor SERR Mask (MSSM): If this bit is set, SERR assertions from
MRL Sensor Change Detected are masked. The state of this bit has no effect
on the state of the MRL Sensor Change Detected bit.
When this bit is clear, then MRL sensor error condition can cause
ERR_FATAL message on the PCI Express* bus provided the SERR enable bit
in the PCICMD register is set or the ERR_FATAL enable bit is set in the PCI
Express* capability.
Connected Power Fault Interrupt Mask (CPFIM): If this bit is set, system
interrupts from Connected Power Fault Detected are masked. The state of
this bit has no effect on the state of the Connected Power Fault Detected bit.
136
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
