Register Description
3.7.1.8
Offset 18h: INT_LOC—Interrupt Locator Register
Offset:
Default Value: 00000000h
18 – 1Bh
Attribute: RO
Size: 32 bits
Interrupt locator register for software to easily identify the source of an interrupt.
Bits
Type
Reset
Description
31:8
7:1
RO
RO
0
0
Reserved.
Slot n Interrupt Pending Bits (SNIPB): A set bit in this field indicates an
interrupt pending condition on the associated slot. An interrupt pending
condition occurs when the SHPC detects a Slot Event, and the event’s
Command Complete Interrupt Mask bit (CCIM, bit 2) in the Slot SERR-INT
Mask field is cleared. Multiple bits are set if multiple slots have an interrupt
pending. Clearing all bits in the Slot Event Latch field (SEL, bit) of the slot’s
Logical Slot register (LSR_SLOT, offset 24h) clears that slot’s bit in this field.
0
RO
0
Command Complete Interrupt Pending (CCIP): The state of this bit is 1
when the Command Completion Detected bit (CCIM, bit 2) in the Slot SERR-
INT Mask field (offset 20h) is set indicating a command completion and the
Command Complete Interrupt Mask bit located in the Controller SERR-INT
Enable register (SERR_INT, offset 20h) is cleared.
3.7.1.9
Offset 1Ch: SERR_LOC—SERR Locator Register
Offset:
Default Value: 00000000h
1C – 1Fh
Attribute: RO
Size: 32 bits
System Interrupt locator register for software to easily identify the source of interrupt.
Bits
Type
Reset
Description
31:8
7:1
RO
RO
0
0
Reserved.
Slot n SERR Pending (SNSP): A set bit in this field indicates an SERR
pending condition on the associated slot. An SERR pending condition occurs
when the SHPC detects a slot event capable of generating an SERR and that
event’s SERR Mask bit in the Slot SERR-INT Mask field is cleared. Multiple
bits are set if multiple slots have an SERR pending. Clearing all bits in the
slot’s Slot Event Latch field that are capable of generating an SERR clears
that slot’s bit in this field.
0
RO
0
Arbiter SERR Pending (ASP): The state of this bit is 1 when the Arbiter
Timeout Detected bit (ATD, bit 17) in the Controller SERR-INT Enable register
(SERR_INT, offset 20h) is set and the Arbiter SERR Mask bit (ASM, bit 3) is
cleared.
Intel® 6700PXH 64-bit PCI Hub Datasheet
133
INTEL [ INTEL ]
