Register Description
3.7.1.10
Offset 20h: SERR_INT—Controller SERR_INT
Enable Register
Offset:
Default Value: 0000000Fh
20–23h
Attribute: RW, RWC, RO
Size: 32 bits
This register enables and disables SERR and System generation and reports global controller
events.
Bits
Type
Reset
Description
31:18
17
RO
0
0
Reserved.
RWC
Arbiter Timeout Detected (ATD): This bit is set when the SHPC detects an
arbiter timeout.
16
RWC
0
Command Completion Detected (CCD): This bit is set when the Controller
Busy bit (CB, bit 0) in the Controller Command Status register
(CONT_COMMAND_STS, offset 16h) transitions from 1 to 0 (indicating a
command completion).
15:4
3
RO
0
1
Reserved.
RW
Arbiter SERR Mask (ASM): When this bit is set, arbiter timeout SERRs are
masked. This bit is a mask and does not affect whether the Arbiter Timeout
Detected bit (bit 17 of this register) is set. When this mask is cleared and the
global SERR mask (bit 1 below) is clear, arbiter timeout error will cause
ERR_NONFATAL message on the PCI Express* bus, provided the SERR
enable bit is set in the PCICMD register or the nonfatal message enable bit is
set in the PCI Express* capability.
2
RW
1
Command Complete Interrupt Mask (CCIM): When this bit is set, command
Completion Interrupts are masked. This bit is a mask and does not affect
whether the Command Completion Detected bit (CCD, bit 16 of this register)
is set.
1
0
RW
RW
1
1
Global SERR Mask (GSM): When this bit is set, SERR generation from the
SHPC is masked.
Global Interrupt Mask (GIM): When this bit is set, System Interrupt
generation by the SHPC is masked. This bit is a mask and does not affect any
bits in the Interrupt Locator register. This bit has no effect on whether the
Wakeup Signal is asserted.
3.7.2
Offset 24h – 40h: Logical Slot Registers (LSR) 1 to 6
Software uses the Logical Slot Register for the following:
• Current status of the slot
• Configure system interrupts and system errors generated by the slots
• Detect pending events on the slots
Each Logical Slot Register is formatted as follows and is described in further detail below.
31
24
23
16
15
0
Slot SERR-INT Mask
Slot Event Latch
Slot Status
134
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
