Register Description
3.7.1.6
Offset 14h: CONT_COMMAND—Controller
Command Register
Offset:
Default Value: 0000h
14–15h
Attribute: RW, RO
Size: 16 bits
Bits
Type
Reset
Description
15:13
12:8
RO
0
0
Reserved.
RW
Target Slot (TS): This field selects the target slot for a Slot Operation
command. For example, writing a 2 to this field would select the 2nd slot for the
Slot Operation command. Software is permitted to write the Command Code
and Target Slot fields simultaneously.
However, software is not required to write these fields simultaneously. If the
fields are not written simultaneously, the Slot Operation command targets the
slot associated with the current value in this register. If the command is not a
Slot Operation command, this field is ignored. When this field is read, it returns
the value that was last written to it, even after the command has completed.
7:0
RW
0
Command Code (CCODE): Command to be executed by the SHPC. Writing
to this field triggers the SHPC to begin executing the command. Refer to the
Standard Hot-Plug Controller and Subsystem Specification, Rev 1.0 for
command encodings. When read, this field returns the command code that
was last written to it, even after the command has completed.
3.7.1.7
Offset 16h: CONT_COMMAND_STS—Controller
Command Status Register
Offset:
Default Value: 0000h
16–17h
Attribute: RO
Size: 16 bits
Bits
Type
Reset
Description
15:4
3:1
RO
RO
0
0
Reserved.
Controller Command Error Code (CCEC): This field shows the result of the
last command completed by the SHPC. This field is updated when the
Controller Busy bit (offset 16-17h, bit 0) transitions from 1 to 0 (indicating a
command completion). If the command failed, the appropriate bit is set. If
none of the bits in this field are set, the command completed successfully.
0
RO
0
Controller Busy (CB): This bit changes from 0 to 1 when a command code is
written to the Controller Command register (CONT_COMMAND, offset 14h). It
stays set until the SHPC has completed executing the command. The SHPC
ignores writes to the Controller Command register (CONT_COMMAND, offset
14h) while this bit is set.
This bit changes from 1 to 0 when the SHPC finishes executing a command.
The SHPC must not set this bit for any other reason. For example, this bit
must not be set to 1 when the SHPC automatically powers down the slot in
response to detecting a MRL open event.
132
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
