Register Description
3.7.1.3
Offset 10h: SBUS_CONFIG
Offset:
Default Value: 00h
10h
Attribute: RO
Size: 16 bits
This register reflects the current speed and mode of PCI bus.
Bits
Type
Reset
Description
15:3:
2:0
RO
RO
0
0
Reserved.
Current Bus Segment Speed/Mode – Indicates the current speed
and mode at which the PCI bus segment is operating.
000 : 33 MHz Conv
001 : 66 MHz Conv
010 : 66 MHz PCI-X Mode
011 : 100 MHz PCI-X Mode
100 : 133 MHz PCI-X Mode
Others : Reserved
3.7.1.4
Offset 12h: SHPC_MSI_CNTL—SHPC
MSI Control Register
Offset:
Default Value: 00h
12h
Attribute: RO
Size: 8 bits
This register indicates the specific message number that will be used by the SHPC to signal an
interrupt when using Message Signaled Interrupts (MSI).
Bits
Type
Reset
Description
7:5
4:0
RO
RO
0
0
Reserved.
SHPC Interrupt Message Number (SHPC_IMN): Reflects the Multiple
Message Enable field (MMEN, bits 6:4) of the MSI Capability Control register
(MSI_MCNTL, offset 5Eh).
3.7.1.5
Offset 13h: SHPC_PROG_IF—SHPC
Programming Interface Register
Offset:
Default Value: 01h
13h
Attribute: RO
Size: 8 bits
Identifies the format of the working register set.
Bits
Type
Reset
Description
7:0
RO
0
SHPC Programming Interface – Identifies the format of the SHPC Working
Register set. A value of 01h identifies the SHPC Working Register set format
defined in 1.0 specification.
Intel® 6700PXH 64-bit PCI Hub Datasheet
131
INTEL [ INTEL ]
