Electrical, Power, and Thermal
Table 4-4.
Power Values for x4 DIMMs (Sheet 2 of 3)
533 MHz
Symbol
Idd_Active_
2
Conditions
Active Power, data pass
through
L0 state.
50% DRAM BW to downstream
DIMM, 67% read, 33% write.
Primary and Secondary
channels enabled
CKE high. Command and
address lines stable.
DRAM clock active.
Power
Supply
@1.5 V
@1.8 V
@3.3 V
Thermal
Design
2.9
0.9
Max
Current
3.2
0.9
667 MHz
Thermal
Design
3.3
0.9
Max
Current
3.7
0.9
Units
A
A
A
Idd_Active_2 Total Power
Idd_Training
(for AMB
spec, Not in
SPD)
Training
Primary and Secondary
channels enabled.
100% toggle on all channel
lanes
DRAMs idle. 0 BW.
CKE high, Command and
address lines stable.
DRAM clock active.
@1.5 V
@1.8 V
@3.3 V
5.5
3.5
0.9
6.1
4.0
0.9
W
A
A
A
Idd_Training Total Power
Idd_IBIST
(for AMB
spec, Not in
SPD)
IBIST
Over all IBIST modes
DRAM Idle (0 BW)
Primary channel Enabled
Secondary channel Enabled
CKE high. Command and
Address lines stable
DRAM clock active
@1.5 V
@1.8 V
@3.3 V
3.8
0.9
4.5
0.9
W
A
A
A
Idd_IBIST Total Power
Idd_MemBI
ST
(for AMB
spec, Not in
SPD)
MemBIST
Over all MemBIST modes
>50% DRAM BW (as dictated
by the AMB)
Primary channel Enabled
Secondary channel Enabled
CKE high. Command and
Address lines stable
DRAM clock active
@1.5 V
@1.8 V
@3.3 V
3.3
2.4
3.8
2.4
W
A
A
A
Idd_MemBIST Total Power
W
42
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL CORPORATION ]
