Electrical, Power, and Thermal
Table 4-4.
Power Values for x4 DIMMs (Sheet 2 of 3)
533 MHz
667 MHz
Power Thermal
Supply Design
Max
Current
Thermal
Design
Max
Current
Symbol
Conditions
Units
Idd_Active_
2
Active Power, data pass
through
L0 state.
50% DRAM BW to downstream @3.3 V
DIMM, 67% read, 33% write.
@1.5 V 2.9
@1.8 V 0.9
3.2
0.9
3.3
0.9
3.7
0.9
A
A
A
Primary and Secondary
channels enabled
CKE high. Command and
address lines stable.
DRAM clock active.
Idd_Active_2 Total Power
Idd_Training Training
5.5
6.1
W
A
@1.5 V
@1.8 V
@3.3 V
3.5
0.9
4.0
0.9
(for AMB
spec, Not in
SPD)
Primary and Secondary
A
channels enabled.
100% toggle on all channel
lanes
A
DRAMs idle. 0 BW.
CKE high, Command and
address lines stable.
DRAM clock active.
Idd_Training Total Power
W
A
Idd_IBIST
IBIST
@1.5 V
@1.8 V
@3.3 V
3.8
0.9
4.5
0.9
(for AMB
spec, Not in
SPD)
Over all IBIST modes
DRAM Idle (0 BW)
Primary channel Enabled
Secondary channel Enabled
A
A
CKE high. Command and
Address lines stable
DRAM clock active
Idd_IBIST Total Power
W
A
Idd_MemBI
ST
MemBIST
Over all MemBIST modes
@1.5 V
@1.8 V
@3.3 V
3.3
2.4
3.8
2.4
A
(for AMB
spec, Not in
SPD)
>50% DRAM BW (as dictated
by the AMB)
Primary channel Enabled
A
Secondary channel Enabled
CKE high. Command and
Address lines stable
DRAM clock active
Idd_MemBIST Total Power
W
42
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
