Electrical, Power, and Thermal
4.2
FB-DIMM Electrical Timing Specifications
The FB-DIMM Channel link electrical interface is more completely described in the High
Speed Differential Point-to-Point Link at 1.5V for Fully Buffered DIMM specification.
Refer to this document for recommended operating conditions.
Table 4-5 contains the FB-DIMM electrical timing specifications.
Table 4-5.
AMB FB-DIMM Timing/Electrical
Symbol
Parameter
Units
Min
Typ
Max
Notes
tEI Propagate
tEID
EI Assertion Pass-Thru Timing
EI Deassertion Pass-Thru Timing
EI Assertion Duration
clks
clks
4
tBitLock
tEI
clks
100
1
1
1
tBitLock
tFrameLock
Bit Lock Interval
frames
frames
119
154
Frame Lock Interval
Notes:
1.
2.
Defined in FB-DIMM Architecture and Protocol Spec
Clocks defined as core clocks = 2x SCLK input
Table 4-6.
AMB FB-DIMM Latency
Date
Rate
Symbol
tC2D_AMB
Parameter
Min
Max
Units
Comments
CMD2DATA = 0x36
CMD2DATA = 0x40
533
667
533
667
533
667
533
667
533
667
18.7
16.2
20.5
17.7
0x36
0x40
0.9
22.3
19
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
tC2D_AMB
CMD2DATA
tRESAMPLE
tRESYNC
CMD2DATA = 0x40
CMD2DATA = 0x46
24.2
20.5
0x48
0x50
1.6
R/C B
R/C B
Resample Delay
1
1
2
2
0.9
1.4
Resync Delay
2.3
3.9
2
3.2
Note:
1.
tRESAMPLE is the delay from the southbound input to the southbound output, or the northbound input to
the northbound output when in resample mode, measured from the center of the data eye.
tRESYNC is the delay from the southbound input to the southbound output, or the northbound input to the
northbound output when in resync mode, measured from the center of the data eye.
2.
.
Figure 4-1. Latency Timing Diagrams
11
5
1
6
2
7
3
9
5
10 11
1
2
3
4
0
8
4
0
Receiver Input
11
6
7
9
10 11
8
Transmit Output
tRESAMPLE
tRESYNC
44
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
