Electrical, Power, and Thermal
Table 4-3.
Power Values for x8 DIMMS (Sheet 2 of 3)
533 MHz
667 MHz
Power
Supply
Thermal
Design
Max
Current
Thermal
Design
Max
Current
Symbol
Conditions
Units
Notes
Idd_TDP_1 Total Power
5.8
6.4
W
A
Idd_Active_1
Active Power
L0 state.
@1.5 V
@1.8 V
@3.3 V
3.1
1.2
3.4
1.3
3.6
1.2
3.9
1.3
A
50% DRAM BW, 67%
read, 33% write.
A
Primary and Secondary
channels enabled.
DRAM clock active, CKE
high.
Idd_Active_1 Total Power
6.4
2.9
0.6
7.1
3.3
0.6
W
A
Idd_Active_2
Active Power, data pass @1.5 V
through
3.2
0.7
3.7
0.7
@1.8 V
A
L0 state.
50% DRAM BW to
@3.3 V
A
downstream DIMM,
67% read, 33% write.
Primary and Secondary
channels enabled
CKE high. Command
and address lines
stable.
DRAM clock active.
Idd_Active_2 Total Power
5.0
5.6
W
A
Idd_Training
Training
@1.5 V
@1.8 V
@3.3 V
3.5
0.7
4.0
0.7
(for AMB spec,
Not in SPD)
Primary and Secondary
channels enabled.
A
100% toggle on all
channel lanes
A
DRAMs idle. 0 BW.
CKE high, Command
and address lines
stable.
DRAM clock active.
Idd_Training Total Power
W
A
Idd_IBIST
IBIST
@1.5 V
@1.8 V
@3.3 V
3.8
0.7
4.5
0.7
(for AMB spec,
Not in SPD)
Over all IBIST modes
DRAM Idle (0 BW)
A
A
Primary channel
Enabled
Secondary channel
Enabled
CKE high. Command
and Address lines stable
DRAM clock active
Idd_IBIST Total Power
W
Intel® 6400/6402 Advanced Memory Buffer Datasheet
39
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