Electrical, Power, and Thermal
Table 4-4 contains the AMB Power Specification Parameters for the Advanced Memory
Buffer part in normal mode.
Table 4-4.
Power Values for x4 DIMMs (Sheet 1 of 3)
533 MHz
667 MHz
Power Thermal
Supply Design
Max
Current
Thermal
Design
Max
Current
Symbol
Conditions
Units
Idd_Idle_0
Idle Current, single or last
DIMM
L0 state, idle (0 BW)
Primary channel enabled,
Secondary Channel Disabled
@1.5 V 2.1
@1.8 V 0.9
@3.3 V
2.2
0.9
2.4
0.9
2.6
0.9
A
A
A
CKE high. Command and
address lines stable.
DRAM clock active.
Idd_Idle_0 Total Power
3.9
@1.5 V 2.7
@1.8 V 0.9
@3.3 V
4.4
3.1
0.9
W
A
Idd_Idle_1 Idle Current, first DIMM
3.0
0.9
3.4
0.9
L0 state, idle (0 BW)
Primary and Secondary
channels enabled
A
A
CKE high. Command and
address lines stable.
DRAM clock active.
Idd_Idle_1 Total Power
4.9
@1.5 V 2.4
@1.8 V 1.5
@3.3 V
5.5
2.8
1.5
W
A
Idd_TDP_0
Active Power, TDP BW, Single
or Last DIMM
2.6
1.6
3.0
1.6
A
L0 state
TDP Channel BW = 2.0GB/
s@533; 2.4GB/s@667;
(for AMB
spec, Not in
SPD)
A
DIMM BW = 2.0GB/s@533;
2.4GB/s@667;
67% read, 33% write.
Primary channel Enabled
Secondary channel Disabled
CKE high. Command and
Address
Idd_TDP_0 Total Power
5.9
@1.5 V 3.0
@1.8 V 1.3
@3.3 V
6.5
3.5
1.3
W
A
Idd_TDP_1
Active Power, TDP BW, First
DIMM
3.3
1.4
3.8
1.4
A
L0 state
TDP Channel BW = 2.0GB/
s@533; 2.4GB/s@667;
(for AMB
spec, Not in
SPD)
A
DIMM BW =2/3 Channel BW =
1.3GB/s@533; 1.6GB/s@667;
67% read, 33% write.
Primary channel Enabled
Secondary channel Enabled
CKE high. Command and Ad
Idd_TDP_1 Total Power
6.3
@1.5 V 3.1
@1.8 V 1.6
@3.3 V
6.9
3.6
1.6
W
A
Idd_Active_
1
Active Power
L0 state.
3.4
1.7
3.9
1.7
A
50% DRAM BW, 67% read,
33% write.
A
Primary and Secondary
channels enabled.
DRAM clock active, CKE high.
Idd_Active_1 Total Power
6.9
7.6
W
Intel® 6400/6402 Advanced Memory Buffer Datasheet
41
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