Electrical, Power, and Thermal
contains the AMB Power Specification Parameters for the Advanced Memory
Buffer part in normal mode.
Table 4-4.
Power Values for x4 DIMMs (Sheet 1 of 3)
533 MHz
Symbol
Idd_Idle_0
Conditions
Idle Current, single or last
DIMM
L0 state, idle (0 BW)
Primary channel enabled,
Secondary Channel Disabled
CKE high. Command and
address lines stable.
DRAM clock active.
Power
Supply
@1.5 V
@1.8 V
@3.3 V
Thermal
Design
2.1
0.9
Max
Current
2.2
0.9
667 MHz
Thermal
Design
2.4
0.9
Max
Current
2.6
0.9
Units
A
A
A
Idd_Idle_0 Total Power
Idd_Idle_1
Idle Current, first DIMM
L0 state, idle (0 BW)
Primary and Secondary
channels enabled
CKE high. Command and
address lines stable.
DRAM clock active.
@1.5 V
@1.8 V
@3.3 V
3.9
2.7
0.9
3.0
0.9
4.4
3.1
0.9
3.4
0.9
W
A
A
A
Idd_Idle_1 Total Power
Idd_TDP_0
(for AMB
spec, Not in
SPD)
Active Power, TDP BW, Single
or Last DIMM
L0 state
TDP Channel BW = 2.0GB/
s@533; 2.4GB/s@667;
DIMM BW = 2.0GB/s@533;
2.4GB/s@667;
67% read, 33% write.
Primary channel Enabled
Secondary channel Disabled
CKE high. Command and
Address
@1.5 V
@1.8 V
@3.3 V
4.9
2.4
1.5
2.6
1.6
5.5
2.8
1.5
3.0
1.6
W
A
A
A
Idd_TDP_0 Total Power
Idd_TDP_1
(for AMB
spec, Not in
SPD)
Active Power, TDP BW, First
DIMM
L0 state
TDP Channel BW = 2.0GB/
s@533; 2.4GB/s@667;
DIMM BW =2/3 Channel BW =
1.3GB/s@533; 1.6GB/s@667;
67% read, 33% write.
Primary channel Enabled
Secondary channel Enabled
CKE high. Command and Ad
@1.5 V
@1.8 V
@3.3 V
5.9
3.0
1.3
3.3
1.4
6.5
3.5
1.3
3.8
1.4
W
A
A
A
Idd_TDP_1 Total Power
Idd_Active_
1
Active Power
L0 state.
50% DRAM BW, 67% read,
33% write.
Primary and Secondary
channels enabled.
DRAM clock active, CKE high.
@1.5 V
@1.8 V
@3.3 V
6.3
3.1
1.6
3.4
1.7
6.9
3.6
1.6
3.9
1.7
W
A
A
A
Idd_Active_1 Total Power
6.9
7.6
W
Intel® 6400/6402 Advanced Memory Buffer Datasheet
41
INTEL [ INTEL CORPORATION ]
