Registers
14.6.1.11 DRRTC00: Receive Enable Reference Output Timing Control Register
This register determines DQS12, 3, 11, 2, 10, 1, 9, & 0 input buffer enable timing delay
Device:
NodeID
Function: 4
Offset:
Bit
A4h
Attr
Default
Description
31:24
23:16
15:8
7:0
RWST
RWST
RWST
RWST
20h
20h
20h
20h
RCVEN1203: receiver enable delay for DQS12 and 3
RCVEN1102: receiver enable delay for DQS11 and 2
RCVEN1001: receiver enable delay for DQS10 and 1
RCVEN0900: receiver enable delay for DQS9 and 0
14.6.1.12 DRRTC01: Receive Enable Reference Output Timing Control Register
This register determines DQS16, 7, 15, 6, 14, 5, 13, & 4 input buffer enable timing
delay.
Device:
NodeID
Function: 4
Offset:
Bit
A8h
Attr
Default
Description
31:24
23:16
15:8
7:0
RWST
RWST
RWST
RWST
20h
20h
20h
20h
RCVEN1607: receiver enable delay for DQS16 and 7
RCVEN1506: receiver enable delay for DQS15 and 6
RCVEN1405: receiver enable delay for DQS14 and 5
RCVEN1304: receiver enable delay for DQS13 and 4
14.6.1.13 DRRTC02: Receive Enable Reference Output Timing Control Register
This register determines DQS17 & 8 input buffer enable timing delay.
Device:
NodeID
Function: 4
Offset:
C4h
Bit
Attr
Default
Description
7:0
RWST
20h
RCVEN1708: receiver enable delay for DQS17 and 8
14.6.1.14 DQS Calibration Registers
The DQSOFCS is a group of six registers that control the fine delay used to center DQS
edges to the DQ data eye during read operations. There is a delay entry for each nibble
of the DDR data bus for each rank. The coarse delay is controlled by the DRAMDLLC
register. The equations for the fine and coarse delays are shown below. Note that
“Delay Element” and “Delay_Uncomp” are defined in the DRRTC register section. Also
note that there is a separate coarse delay control for each “chunk” of the DDR I/O
cluster as defined in the DRAMDLLC register section.
slvlen_not_at_max[m] = DRAMDLLC.SLVLENm[2:0] < 7; where m is the DDR I/O
cluster chunk number
increment_slvlen[i,n] = slvlen_not_at_max AND ( DQSOFCSi.DQSn[3:0] > 7 ); where i
and n are the DQSOFCS register and DQS field numbers respectively
214
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
