Registers
slvlen[i,m,n] = DRAMDLLC.SLVLENm[2:0] + increment_slvlen[i,n]
Programable_Delay[i,m,n] = ( Delay Element ) * ( slvlen[i,m,n] + 0.5 +
DQSOFCSi.DQSn[2:0]/8 )
DQS_Delay[i,m,n] = Delay_Uncomp + Programmable_Delay[i,m,n]
Note: these registers may have to be saved and restored on S3
14.6.1.15 DQSOFCS00: DQS Calibration Register
This register determines DQS12, 3, 11, 2, 10, 1, 9, & 0 fine DQS delay when reading
from rank 0.
Device:
NodeID
Function: 4
Offset:
Bit
B4h
Attr
Default
Description
31:28
27:24
23:20
19:16
15:12
11:8
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
0h
0h
0h
0h
0h
0h
0h
0h
DQS12: Fine delay
DQS03: Fine delay
DQS11: Fine delay
DQS02: Fine delay
DQS10: Fine delay
DQS01: Fine delay
DQS09: Fine delay
DQS00: Fine delay
7:4
3:0
14.6.1.16 DQSOFCS01: DQS Calibration Register
This register determines DQS16, 7, 15, 6, 14, 5, 13, & 4 fine DQS delay when reading
from rank 0.
Device:
NodeID
Function: 4
Offset:
Bit
B8h
Attr
Default
Description
31:28
27:24
23:20
19:16
15:12
11:8
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
0h
0h
0h
0h
0h
0h
0h
0h
DQS16: Fine delay
DQS07: Fine delay
DQS15: Fine delay
DQS06: Fine delay
DQS14: Fine delay
DQS05: Fine delay
DQS13: Fine delay
DQS04: Fine delay
7:4
3:0
Intel® 6400/6402 Advanced Memory Buffer Datasheet
215
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