Registers
The DRRTC is a set of three registers with DQS receiver enable window timing control
for each byte on the DDR data bus. There is a single control for each byte for both
ranks. A correct register setting will delay the start of the enable window so that it
coincides with the middle of the DQS pre-amble. Enabling the window before or after
the pre-amble would cause valid DQS edges to be missed or invalid edges or noise to
be received.
The range of the enable delay, controlled by the DRRTC registers, is eight cycles, with a
granularity defined by the SPDPAR06CUR.MASTCNTL register. The delay is measured
from the AMC core clock edge that launches a “read” command on the DDR command
bus. The minimum delay is equal to the DDR SDRAM read latency defined in the
DRC.CL and DRC.AL register fields. The maximum delay is the read latency plus eight
cycles. In addition to these major sources of delay, there is also a small
“uncompensated delay” as shown in the formulas below.
The RCVEN fields of the DRRTC register control the delay as follows: bits [7:5] control
whole clock increments, bits [4:3] control in quarter clock increments, and bits [2:0]
control the sub-quarter cycle increments. Setting RCVEN to 0x0 produces the minimum
delay, and 0xFF sets the maximum delay. The sub-quarter cycle delay is defined by the
equations and “RCVEN_OUT” lookup table below:
Delay_Uncomp = 100ps; Note: estimate only
Delay Element = (quarter CMDCLK period - Delay_Uncomp) / ( MASTCNTL + 0.5)
sub quarter cycle delay = Delay_Uncomp + (Delay Element * RCVEN_OUT[2:0])
RCVEN_OUT Lookup Table
DRRTC RCVEN [2:0]
SPDPAR06CUR
MASTCNTL]
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
4
3
2
1
0
5
5
4
3
2
2
1
0
4
4
3
3
2
1
1
0
3
3
2
2
1
1
0
0
2
2
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
For example, if the SPDPAR06CUR.MASTCNTL is set to 0x7, the receiver enable delay
can be varied over eight cycle in 256 steps, one step for each DRRTC RCVEN setting. If
SPDPAR06CUR.MASTCNTL is set to 0x3, however, the number of steps is reduced to
128, such that half of the DRRTC RCVEN settings do not produce an increase in delay
from the previous setting.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
213
INTEL [ INTEL ]
