Registers
14.6.1.9
DQSFAIL0: DQS Failure Configuration Register 0
Device:
NodeID
Function: 4
Offset:
Bit
A0h
Attr
Default
Description
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
r1dqs15: rank 1
r1dqs06: rank 1
r1dqs14: rank 1
r1dqs05: rank 1
r1dqs13: rank 1
r1dqs04: rank 1
r1dqs12: rank 1
r1dqs03: rank 1
r1dqs11: rank 1
r1dqs02: rank 1
r1dqs10: rank 1
r1dqs01: rank 1
r1dqs09: rank 1
r1dqs00: rank 1
r0dqs17: rank 0
r0dqs08: rank 0
r0dqs16: rank 0
r0dqs07: rank 0
r0dqs15: rank 0
r0dqs06: rank 0
r0dqs14: rank 0
r0dqs05: rank 0
r0dqs13: rank 0
r0dqs04: rank 0
r0dqs12: rank 0
r0dqs03: rank 0
r0dqs11: rank 0
r0dqs02: rank 0
r0dqs10: rank 0
r0dqs01: rank 0
r0dqs09: rank 0
r0dqs00: rank 0
8
7
6
5
4
3
2
1
0
14.6.1.10 DRRTC: Receive Enable Reference Output Timing Control Registers
Note:
These registers have to be saved and restored on S3.
212
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
