Registers
14.6.1.6
DSRETC: DRAM Self-Refresh Extended Timing and Control
This register sets the timing of operations to different ranks while the auto-refresh FSM
controls the DRAM command bus. This allows power intensive commands to be
staggered. This register also contains the count for the auto-refresh FSM handshake
time out. The FSM will wait a maximum of the time out count before taking control of
the bus and issuing the command sequence to put the DRAMs into self-refresh. The
RSTREQERR bit of the DSREFTC CSR will be set if the time out count is reached.
Device:
NodeID
Function: 4
Offset:
Bit
98h
Attr
Default
Description
31:24
23:16
RV
0h
Reserved
RWST
14h
DRSRENT: dual rank self-refresh entry timing - stagger of commands
between ranks
15:8
7:0
RWST
RWST
14h
FFh
DRARTIM: dual rank auto-refresh timing- stagger of commands
between ranks
TREQERR: reset handshake time out count
(counts in x16 of core clock)
If times out - forces DRAMs into self-reset even if no handshake received
from MemBIST or other logic after link goes into fast reset
14.6.1.7
DQSFAIL
There are two DQSFAIL registers that contain a total of 36 individual DQS failure status
bits. There is one status bit for each DQS signal pair on each rank. These bits are set
automatically by hardware during the receiver enable calibration if a valid DQS
waveform is not detected. Hardware will not clear any bits that are set prior to the
calibration even if a valid waveform is detected. Hardware uses the DQSFAIL
information to exclude calibration data during the data gathering portion and/or the
data analysis portion of the both the receiver enable and DQS delay calibrations. This
prevents a failed DQS pin from corrupting the calibration of neighboring functional DQS
pins that may share internal logic resources with a failing DQS pin.
14.6.1.8
DQSFAIL1: DQS Failure Configuration Register 1
Device:
NodeID
Function: 4
Offset:
Bit
9Ch
Attr
Default
Description
7:4
3
RV
0h
0
Reserved
RWST
RWST
RWST
RWST
r1dqs17: rank 1
r1dqs08: rank 1
r1dqs16: rank 1
r1dqs07: rank 1
2
0
1
0
0
0
Intel® 6400/6402 Advanced Memory Buffer Datasheet
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INTEL [ INTEL ]
