Registers
DCALDATA Receiver Enable “First edge position” byte detail
Description
Bit
7:0
At the end of a successful calibration, this register holds the DRRTC setting that enables the DQS
receiver as close as possible to but no earlier than the first rising DQS transition after the preamble. At
the start of the calibration, this register is loaded with a value of 0xFF. During the calibration, while
the “strobe toggle status” bit is low, this register will be updated with the DRRTC value for the current
calibration step if the DQS is found to have a value of zero. After “strobe toggle status” goes high, this
register will be updated with the DRRTC value when the DQS is found to have a value of one at a
calibration step. This register will no longer be updated after the “preamble found status” bit
goes high, so that it will retain the position of the rising DQS edge following immediately after
the preamble.
DCALDATA Receiver Enable “Preamble status” byte detail
Description
Bit
7
Strobe toggle status. Hardware sets this bit if a valid high pulse is found in the strobe waveform. The
requirement is (DCALDATA.First_edge_position - last receiver enable delay value) >
RCVENAC.HWIDTH
6
5
Preamble found status. Hardware sets this bit if the “preamble found” bit asserts at any time during
the calibration.
Preamble found. Last receiver enable delay value meets or exceeds the preamble width requirement
setting.
Hardware sets this bit if: (DCALDATA.First_edge_position - last receiver enable delay value) >
RCVENAC.PWIDTH
4:0
Count of “lows” minus count of “highs” found during one set of repeated tests at the last receiver
enable delay setting. See DCALCSR opmods field for a description of the repeat test function.
DCALDATA DQS Cal Max Delay detail
Bit
Description
7:6
5:0
reserved
At the end of a successful calibration, this field will hold the maximum DQS delay setting that results
in correct data capture in the DDR I/O capture flop. This is the right edge of the DQ data eye. During
the calibration, this field is updated with the DQS delay setting at each calibration step until the
minimum delay setting is found and a subsequent failure to capture correct read data occurs.
Table 14-16.Functional Characteristics of DCALDATA for HVM Algorithms
Byte
I/O Loopback
DLL BIST
71:3
6
Not used
Not used
35
34
33
32
31
30
First “All Bits Failed” position and Status DQS17
First “Any Bit Failed” Position and Status DQS17
First “All Bits Failed” position and Status DQS8
First “Any Bit Failed” Position and Status DQS8
First “All Bits Failed” position and Status DQS16
First “Any Bit Failed” Position and Status DQS16
Core Counter DQS17
Core Counter DQS8
Core Counter DQS16
208
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
