Registers
Table 14-16.Functional Characteristics of DCALDATA for HVM Algorithms
Byte
I/O Loopback
DLL BIST
Core Counter DQS7
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
First “All Bits Failed” position and Status DQS7
First “Any Bit Failed” Position and Status DQS7
First “All Bits Failed” position and Status DQS15
First “Any Bit Failed” Position and Status DQS15
First “All Bits Failed” position and Status DQS6
First “Any Bit Failed” Position and Status DQS6
First “All Bits Failed” position and Status DQS14
First “Any Bit Failed” Position and Status DQS14
First “All Bits Failed” position and Status DQS5
First “Any Bit Failed” Position and Status DQS5
First “All Bits Failed” position and Status DQS13
First “Any Bit Failed” Position and Status DQS13
First “All Bits Failed” position and Status DQS4
First “Any Bit Failed” Position and Status DQS4
First “All Bits Failed” position and Status DQS12
First “Any Bit Failed” Position and Status DQS12
First “All Bits Failed” position and Status DQS3
First “Any Bit Failed” Position and Status DQS3
First “All Bits Failed” position and Status DQS11
First “Any Bit Failed” Position and Status DQS11
First “All Bits Failed” position and Status DQS2
First “Any Bit Failed” Position and Status DQS2
First “All Bits Failed” position and Status DQS10
First “Any Bit Failed” Position and Status DQS10
First “All Bits Failed” position and Status DQS1
First “Any Bit Failed” Position and Status DQS1
First “All Bits Failed” position and Status DQS9
First “Any Bit Failed” Position and Status DQS9
First “All Bits Failed” position and Status DQS0
First “Any Bit Failed” Position and Status DQS0
Core Counter DQS15
Core Counter DQS6
Core Counter DQS14
Core Counter DQS5
Core Counter DQS13
Core Counter DQS4
Core Counter DQS12
Core Counter DQS3
Core Counter DQS11
Core Counter DQS2
Core Counter DQS10
Core Counter DQS1
Core Counter DQ9
Core Counter DQS0
8
7
6
5
4
3
2
1
0
DCALDATA I/O Loopback “Any Bit Failed” detail
Bit
Description
7
First “First Any bit Failed” Nibble. This bit is set if the nibble associated with this register is one of the
first to fail to capture data correctly during the test.
6
reserved
5:0
At the end of the test, this field will contain the minimum DQS delay setting that results in one or
more bits of a burst to be captured incorrectly.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
209
INTEL [ INTEL ]
