Registers
Table 14-13.BL8 Column and Chunk Correspondence to DRAM Address
Register Bit Location
DRAM Col Address
Data Chunk
12 11 10
9
8
9
7
8
6
7
5
6
4
5
3
4
2
3
1
0
1
14 13 12 11
2
X
• where the auto-precharge address bit 10 is assumed zero
• since data is logged in 144 bits (two chunks), Data chunk address bit zero is not
needed
14.5.2.4
MB_START_ADDR: Memory Test Start Address
MB_END_ADDR row and column address must be larger than MB_START_ADDR row
and column address in either increasing or deceasing address mode.
During FastX, FastY and FastXY operation, only one memory bank is tested. Specify the
desired bank in MB_START_ADDR[2:0]. MB_END_ADDR[2:0] is ignored.
This register is only used when MBCSR.atype = 2b’10, and when MBCSR.algo is
non-zero.
Device:
NodeID
Function: 3
Offset:
Bit
9Ch
Attr
Default
Description
31:16 RWST
0000h ROW: MemBIST Start Row Address 15:0
Reserved
15
RV
0
14:3
RWST
0000h COL: MemBIST Start Column Address
BL8 [14:3] <==> Column Address 15:11, 9:3
BL4 [14:3] <==> Column Address 14:11, 9:2
2:0
RWST
000
BA: MemBIST Start Bank Address 2:0
14.5.2.5
MB_END_ADDR: Memory Test End Address
This register is only used when MBCSR.atype = 2b’10, and when MBCSR.algo is
non-zero.
Device:
NodeID
Function: 3
Offset:
Bit
A0h
Attr
Default
Description
31:16 RWST
0000h ROW: MemBIST End Row Address 15:0
Reserved
15
RV
0
14:3
RWST
0000h COL: MemBIST End Column Address
BL8 [14:3] <==> Column Address 15:11, 9:3
BL4 [14:3] <==> Column Address 14:11, 9:2
2:0
RWST
000
BA: MemBIST End Bank Address 2:0
196
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
