Registers
Device:
NodeID
Function: 3
Offset:
40h
Bit
Attr
Default
Description
ALGO: Embedded Algorithm selection:
Embedded Algorithm selection:
26:24
RW
000
000 => No embedded algorithm is selected. Normal command will be executed
from the selection of MBCSR bits field [5:4]
001 => Scan: ^ (WD1); ^(RD2); ^ (WI3); ^ (RI4)
010 => Undefined
011 => Data Retention Write or Init: ^ (WD1);
100 => Data Retention Read : ^ (RD2);
101 => Mats +: ^(WD1); ^(RD2, WI3); v(RI4, WD5);
110 => March C-: ^(WD1); ^(RD2, WI3); ^(RI4, WD5);
v(RD6, WI7); v(RI8, WD9); v(RD10);
111 => Undefined
Reserved
23:22
21:20
RV
00
00
RW
CS: CS[1:0] selection in MemBIST mode
01: select Rank 0
10: select Rank 1
00: Reserved
11: Reserved
19
RW
RW
0
INVERT: Invert data pattern when data is written out to DRAM.
18:16
000
FIXED: Fixed data pattern selection for MemBIST operation
000 => 0
001 => F
010 => A
011 => 5
100 => C
101 => 3
110 => 9
111 => 6
15
RW
0
ENABLE288: Enable 288 bits user defined pattern for memory fill write only.
There is no data comparison, error logger functions for 288 bits user defined
data.
0 => 144 bits user defined data pattern when MBCSR[9:8] selects user defined
data.
1 => 288 bits user defined data pattern when MBCSR[9:8] selects user defined
data.
14
13
RW
RW
0
0
MBDATA: Selects use of MBDATA for error log field for LFSR, Circular Shift and
user defined data modes. This field has no effect on fixed data patterns.
0 => use MBDATA0/1/2/3/8 for failure data bit location accumulator.
1 => use MBDATA0/1/2/3/8 to log 5 failure addresses.
ABAR: MemBIST output address compliment for FastX, FastY, and FastXY.
Whenever this bit is enabled, Bank, Row, Column address will be inverted on
alternate addresses as described in the MemBIST chapter.
0 => Regular addressing
1 => Dynamic address inversion
12
RW
0
ADIR: Address decode direction for FastX, Fast Y, FastXY
0 => Address increments
1 => Address decrements
192
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
