Registers
Description by mode
(note: MBCSR.dtype, MBCSR.mbdata and MBCSR.enable288 select mode)
Reg
Bit
Offset
Fixed Data
Pattern
144 bit User
Defined Pattern
288 bit User
defined pattern
Circular Shift
LFSR
Late data [31:0]
Failure bit location
accumulator
Fail address 3
Or
Late data [31:0]
Failure bit location Failure bit location Failure bit location
accumulator
Fail address 3
Or
Late data [31:0]
Fail address 3
Or
Late data [31:0]
User defined Late
data [31:0] (1st
burst data)
MBDATA2 31:0 50h
MBDATA1 31:0 4Ch
MBDATA0 31:0 48h
accumulator
accumulator
Early data [63:32] Fail address 2
Failure bit location
accumulator
Fail address 2
Or
Fail address 2
Or
User defined Early
data [63:32]
(1st burst data)
Or
Early data [63:32] Early data [63:32] Early data [63:32]
Failure bit location Failure bit location Failure bit location
accumulator
accumulator
accumulator
Early data [31:0]
Failure bit location
accumulator
Fail address 1
Or
Early data [31:0]
Fail address 1
Or
Early data [31:0]
Fail address 1
Or
Early data [31:0]
User defined Early
data [31:0]
(1st burst data)
Failure bit location Failure bit location Failure bit location
accumulator accumulator accumulator
Note: In the later half part of data burst length 8 test, 144 bits or 288 bits user-defined data pattern will be repeat as the same
sequence of burst length 4.
14.5.2.3.1
MBDATA Failure Address Mapping
To compress the failure address into 32 bits, bits that are always zero are removed
from the logging. These removed bits include AutoPrecharge Column address [10] and
least significant bits assumed by burst length.
Table 14-11.MBDATA Failure Address Register Correspondence to DRAM Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
2
1
9
8
7
6
5
4
3
2
1
0
see description below
Column and Chunk
Bank
Row
BL4: 1 bit chunk indicates the location of 2 failure burst data chunks.
The above Column plus Chunk is equal to DRAM column address as the following:
Table 14-12.BL4 Column and Chunk Correspondence to DRAM Address
1
2
1
1
1
0
Register Bit Location
9
8
9
7
8
6
7
5
6
4
5
3
4
2
3
1
2
0
1
4
1
3
1
2
1
1
DRAM Col Address
Data Chunk
1
X
• where the auto-precharge address bit 10 is assumed zero
• since data is logged in 144 bits (two chunks), address bit zero is not needed
BL8: 2 bit chunk indicates the location of 4 failure burst data chunks.
The above Column plus Chunk is equal to DRAM column address as the following:
Intel® 6400/6402 Advanced Memory Buffer Datasheet
195
INTEL [ INTEL ]
