Registers
Device:
NodeID
Function: 3
Offset:
7Ch
Bit
Attr
Default
Description
3:0
RWST
3h
CL: DRAM CAS Latency [3:0]
Note: This CL value is sampled during TS2 training sequences to set timing for FBD
link data returns. Changes to CL after this time will not effect FBD link data return
timing until the next TS2 sequence following link reset.
14.5.2
Memory BIST Registers
14.5.2.1
MBCSR: MemBIST Control
Architected MemBIST control interface.
Device:
NodeID
Function: 3
Offset:
40h
Bit
Attr
Default
Description
31
RWS
0
START: Start operation:
1 => Set this bit to begin MemBIST execution.
0 => Hardware will clear this bit when MemBIST execution is completed.
30
29
RW
RW
0
0
PF: Fail/Pass indicator:
Write to 0 when start MemBIST. Hardware will set to 1 when a failure is detected.
0 => Pass
1 => Fail
HALT: Halt on Error
0 => Operation will not halt due to a detected error.
1 => Operation will halt after read-compare data error is detected.
MemBIST will complete the current transaction before halting. This may result in
multiple errors being logged.
28
RW
0
ABORT: MemBIST test abort. When test abort bit is set, MBCSR bit 31 (Start
operation, RWS) needs to be set to "0" at the same time to avoid restarting
MemBIST.
0 => Normal operation.
1 => Need to abort the test during MemBIST operation.
If there is any following membist test after the abort test, bit [28] needs to be
cleared.
The Write to set MBCSR.abort must occur at least tRFC after the Write to set
MBCSR.start. Otherwise subsequent MemBIST operations may fail.
tRFC value is set in DAREFTC.trfc (Function3, offset70h, bit field 23:16).
27
RW
0
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Intel® 6400/6402 Advanced Memory Buffer Datasheet
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