Registers
Device:
NodeID
Function: 3
Offset:
Bit
78h
Attr
Default
Description
15:12 RWST
0000
TRC: Trc DRAM activate to another activate delay
0000 => 26
0001 => 25
0010 => 24
0011 => 23
0100 => 22
0101 => 21
0110 => 20
0111 => 19
1000 => 18
1001 => 17
1010 => 16
1011 => 15
1100 => 14
1101 => 13
1110 => 12
1111 => 11
11:10 RWST
00
TRCD: Trcd DRAM RAS# to CAS# delay
00 => 6
01 => 5
10 => 4
11 => 3
If AL >= Trcd, Read/Write command will be issued right after ACT cycle.
9:8
7:0
RWST
RWST
00
TRP: Trp DRAM RAS# to Precharge delay
00 => 6
01 => 5
10 => 4
11 => 3
00h
NOPCNT: Programmable NOP insertion (Device Deselect actually).
Number of Nops will be inserted between read/write commands to slow down
Membist activities in the same page.
Up to 255 clocks NOPs can be programmed to insert delay between read/write
commands. If NOPs delay is programmable less than the required DRAM timing,
Overall NOP delay from command to command will not be seen.
14.5.1.5
DRC: DRAM Controller Mode Register
This register controls the mode of the DRAM Controller.
Device:
NodeID
Function: 3
Offset:
Bit
7Ch
Attr
Default
Description
31:30
29
RV
00
0
Reserved
RW
INITDONE: Initialization Complete. This scratch bit communicates software
state from the AMB to BIOS. BIOS sets this bit to 1 after initialization of the DRAM
memory array is complete. This bit has no effect on AMB operation.
28
RV
0
Reserved
Intel® 6400/6402 Advanced Memory Buffer Datasheet
189
INTEL [ INTEL ]
