Registers
Device:
NodeID
Function: 3
Offset:
Bit
7Ch
Attr
Default
Description
CLKDIS: clock[3:0] output disable
27:24 RWST
0
0
23
RWST
SEQADDR: When set to 1 turns off address balancing on address bit A0 to support
DRAMs programmed for Sequential Burst Type
22
RWST
0
DQSHALFGAIN: - select for DQS differential amplifier gain. When set to 0
the amplifier gain is cut half to support differential strobes for DDR2
Note: the sense of this field is inverted from past DDR designs so that BIOS
supporting generic AMBs do not have to write a “1” to what is a “reserved”
field on other AMBs
21
RW
0
TESTMODE: When set to 1 the LEGSEL output of the DDR comp block selects one
of eight driver legs to enable. This bit can be used in conjunction with the
DRAMISCTL.DRVOVR bits to override the LEGSEL output generated by the comp
block.
20
19
RWST
RWST
0
0
RWPRDIS: Read/Write pointer reset disable
Disables the resetting of DDR cluster FIFO read and write pointers during normal
operation that occurs when a READ command finishes executing and no additional
READ commands are in process.
18
17
RWST
RWST
1
0
ODTZ: On-Die Termination Strength.
“0”
“1”
Disabled
Enabled
HLDDIS: command/address hold disable
Disabling hold will allow the address and bank address pins to revert to all zeros (all
ones on the balanced address copy) during idle cycles. When hlddis is clear, the
addresses retain the value of the last non-idle command cycle in order to reduce
switching on the bus.
16
15
14
13
12
RWST
RW
0
0
0
0
1
BALDIS: command/address balancing disable
CADIS: command/address output disable
CSDIS: chip select output disable
ODTDIS: ODT output disable
RW
RW
RWST
CKEFRCLOW: CKE Force Low
Forces CKE low. Must be cleared to enable normal DDR functionality. This bit
overrides the CKE1 and CKE0 fields described below, and also overrides all channel
commands and other hardware functions that would otherwise affect the state of
the CKE outputs.
11
10
RW
0
0
CKEDIS: CKE output disable
RWST
CKE1: CKE output 1 control and status. Software can write to this bit to change the
state of the CKE 1 output. Hardware will update this bit with the current status of
the CKE1 output two core cycles after a channel command or other hardware
function changes the state of the CKE1 output.
‘1’ = CKE1 pads asserted.
‘0’ = CKE1 pads de-asserted.
9
RWST
0
CKE0: CKE output 0 control and status. Software can write to this bit to change the
state of the CKE 0 output. Hardware will update this bit with the current status of
the CKE 0 output two core cycles after a channel command or other hardware
function changes the state of the CKE 0 output.
‘1’ = CKE0 pads asserted.
‘0’ = CKE0 pads de-asserted.
8
RWST
RWST
0
BL: DRAM burst length.
‘1’ = bl8
‘0’ = bl4
7:4
2h
AL: DRAM Additive Latency [3:0]
Note: This AL value is sampled during TS2 training sequences to set timing for FBD
link data returns. Changes to AL after this time will not effect FBD link data return
timing until the next TS2 sequence following link reset.
190
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
