Registers
14.5
DDR and Miscellaneous Registers (Function 3)
14.5.1
Memory Registers
14.5.1.1
DAREFTC: DRAM Auto-Refresh Timing and Control
Device:
NodeID
Function: 3
Offset:
Bit
70h
Attr
Default
Description
31
30
29
28
RV
0
0
0
0
Reserved
RWST
RWST
RWST
REFDERR: refresh buffer overflow error
REFIERR: buffer count greater than the number of installed ranks
ORIDEHS: override handshake; auto-refresh wins arbitration for
command bus
27:24
23:16
15
RWST
RWST
RW
0
4Eh
0
RBUF: number of pending refreshes for all ranks combined
TRFC: DRAM refresh period
AREFEN: auto-refresh enable
14:0
RWST
0C30h
TREFI: DRAM refresh interval
14.5.1.2
DSREFTC: DRAM Self-Refresh Timing and Control
Device:
NodeID
Function: 3
Offset:
Bit
74h
Attr
Default
Description
23:17
16
RV
0
1
Reserved
RWST
RWST
RWST
RV
DISSREXIT: Disable DRAM Self-Refresh Exit when the link comes up
TXSNR: DRAM Self-Refresh Exit to Non-Read Command Timing
TRP: DRAM Precharge Timing
15:8
7:4
3
56h
Fh
0
Reserved
2:0
RWST
7h
TCKE: DRAM Minimum CKE Pulse Width
14.5.1.3
MTR: Memory Technology Register
This register provides a local definition of the organization of DIMMs. This DRAM
configuration information is used for MemBIST and DDR calibration.
Device:
NodeID
Function: 3
Offset:
Bit
77h
Attr
Default
Description
7
6
RV
0
0
Reserved
RWST
WIDTH: Technology – DRAM data width
Define the data width of SDRAMs within these DIMM’s
0 = x4 (4 bits wide)
1 = x8 (8 bits wide)
186
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
