Registers
14.3.5.2
CMD2DATACUR: Current Value of Command to Data Delay
This register has the current value of the command to data delay.
Device:
NodeID
Function: 1
Offset:
E9h
Bit
Attr
Default
Description
7:4
ROST
0h
DLYFRMS: Number of frames
This specifies full frame delay part of the command to data delay.
0 - 9: Valid delays
10 - 15: Reserved
3:0
ROST
0h
DLYFRAC: Fractional delay of command to data
This specifies fractional frame delay part of the command to data delay.
0 - 11: Specifies the delay in 1UI increments
12 - 15: Reserved
14.3.5.3
C2DINCRNXT: Next Value of Command to Data Delay Increment
This register has the next value of the command to data incremental delay. This will be
used after the next fast reset. This will be used by the last AMB to delay driving the
data beyond that specified in the command to data delay.
Device:
NodeID
Function: 1
Offset:
Bit
EAh
Attr
Default
Description
7:2
1:0
RV
0h
0h
Reserved
RWST
INCRDLY: Incremental Delay for command to data
0 - 3: Specifies the incremental delay in frames
14.3.5.4
C2DINCRCUR: Current Value of Command to Data Delay Increment
This register has the current value of the command to data incremental delay. This will
be used by the last AMB to delay driving the data beyond that specified.
Device:
NodeID
Function: 1
Offset:
Bit
EBh
Attr
Default
Description
7:2
1:0
RV
0h
0h
Reserved
ROST
INCRDLY: Incremental Delay for command to data
0 - 3: Specifies the incremental delay in frames
14.4
Implementation Specific FBD Registers (Function
2)
No register information is available for the implementation specific registers.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
185
INTEL [ INTEL ]
