Switching Characteristics
Page 23
(1)
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
(Part 6 of 7)
Transceiver Speed
Grade 1
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
Inter-transceiver
block transmitter
channel-to-
xN PMA
bonded mode
—
—
500
—
—
500
—
—
500
ps
channel skew
CMU PLL
8500/
Supported Data
Range
—
600
—
12500
600
—
12500
600
—
10312.5
Mbps
(24)
(15)
tpll_powerdown
—
—
1
—
—
—
10
1
—
—
—
10
1
—
—
—
10
µs
µs
(16)
tpll_lock
—
—
—
ATX PLL
VCO
8500/
post-divider 8000
L=2
—
14100 8000
—
12500 8000
—
10312.5
Mbps
(24)
L=4
L=8
4000
2000
—
—
7050
3525
4000
2000
—
—
6600
3300
4000
2000
—
—
6600
3300
Mbps
Mbps
Supported Data
Rate Range
L=8,
Local/Central
Clock Divider
=2
1000
—
1762.5 1000
—
1762.5 1000
—
1762.5
Mbps
(15)
tpll_powerdown
—
—
1
—
—
—
10
1
—
—
—
10
1
—
—
—
10
µs
µs
(16)
tpll_lock
—
—
—
fPLL
Supported Data
Range
3250/
3250/
3250/
—
—
600
1
—
—
600
1
—
—
600
1
—
—
Mbps
µs
3125 (25)
3125 (25)
3125 (25)
(15)
tpll_powerdown
—
—
—
December 2015 Altera Corporation
Stratix V Device Datasheet
INTEL [ INTEL ]
