Switching Characteristics
Page 19
(1)
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
(Part 2 of 7)
Transceiver Speed
Grade 1
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Symbol/
Conditions
Unit
Description
Min
Typ
0 to
–0.5
Max
Min
Typ
0 to
–0.5
Max
Min Typ
Max
0 to
—
Spread-spectrum
downspread
PCIe
—
—
—
—
—
—
%
–0.5
On-chip
termination
—
—
100
—
—
—
—
100
—
—
—
—
100
—
—
resistors (21)
Dedicated
reference
clock pin
1.6
1.6
1.6
(5)
Absolute VMAX
V
RX reference
clock pin
—
—
—
1.2
—
—
—
—
1.2
—
—
—
—
1.2
—
Absolute VMIN
—
–0.4
–0.4
–0.4
V
Peak-to-peak
differential input
voltage
—
200
—
1600
200
—
1600
200
—
1600
mV
Dedicated
reference
clock pin
(2)
(2)
(2)
1050/1000/900/850
1.0/0.9/0.85 (4)
1050/1000/900/850
1.0/0.9/0.85 (4)
1050/1000/900/850
1.0/0.9/0.85 (4)
mV
V
V
ICM (AC
coupled) (3)
RX reference
clock pin
HCSL I/O
standard for
PCIe
VICM (DC coupled)
250
—
550
250
—
550
250
—
550
mV
reference
clock
100 Hz
1 kHz
—
—
—
—
—
—
—
—
—
—
-70
-90
—
—
—
—
—
—
—
—
—
—
-70
-90
—
—
—
—
—
—
—
—
—
—
-70
-90
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Transmitter
REFCLK Phase
Noise
10 kHz
100 kHz
≥1 MHz
-100
-110
-120
-100
-110
-120
-100
-110
-120
(622 MHz) (20)
Transmitter
REFCLK Phase
Jitter
10 kHz to
1.5 MHz
(PCIe)
ps
(rms)
—
—
—
3
—
—
—
3
—
—
—
3
(100 MHz) (17)
180
0
1%
1800
1%
1800
1%
(19)
RREF
—
—
—
—
Transceiver Clocks
PCIe
Receiver
Detect
100
or
125
100
or
125
100
or
125
fixedclkclock
frequency
—
—
—
—
—
—
MHz
December 2015 Altera Corporation
Stratix V Device Datasheet
INTEL [ INTEL ]
