Switching Characteristics
Page 25
Table 24 shows the maximum transmitter data rate for the clock network.
(1)
Table 24. Clock Network Maximum Data Rate Transmitter Specifications
ATX PLL
CMU PLL (2)
fPLL
Non-
bonded
Mode
Non-
Non-
Bonded
Mode
(Gbps)
Bonded
Mode
(Gbps)
Bonded
Mode
(Gbps)
Clock Network
Channel bonded
Channel bonded
Channel
Span
Span
Mode
(Gbps)
Span
Mode
(Gbps)
(Gbps)
x1 (3)
x6 (3)
14.1
—
—
6
6
12.5
—
—
6
6
3.125
—
—
3
6
14.1
12.5
3.125
x6 PLL
Side-
wide
Side-
wide
—
—
14.1
8.0
—
—
12.5
5.0
—
—
—
—
—
—
Feedback (4)
xN (PCIe)
8
8
Up to 13
channels
above
and
below
PLL
8.0
—
8.0
Up to 13
channels
above
and
below
PLL
Up to 13
channels
above
and
below
PLL
xN (Native PHY IP)
7.99
7.99
3.125
3.125
Up to 7
channels
above
and
8.01 to
9.8304
below
PLL
Notes to Table 24:
(1) Valid data rates below the maximum specified in this table depend on the reference clock frequency and the PLL counter settings. Check the
MegaWizard message during the PHY IP instantiation.
(2) ATX PLL is recommended at 8 Gbps and above data rates for improved jitter performance.
(3) Channel span is within a transceiver bank.
(4) Side-wide channel bonding is allowed up to the maximum supported by the PHY IP.
December 2015 Altera Corporation
Stratix V Device Datasheet
INTEL [ INTEL ]
