Page 26
Switching Characteristics
Table 25 shows the approximate maximum data rate using the standard PCS.
(1), (3)
Table 25. Stratix V Standard PCS Approximate Maximum Date Rate
PMA Width
20
40
20
20
16
32
16
16
10
20
10
10
8
8
8
Transceiver
Speed Grade
(2)
Mode
PCS/Core Width
16
C1, C2, C2L, I2, I2L
core speed grade
1
2
12.2
12.2
9.8
11.4
11.4
9.0
9.76
9.76
7.84
8.5
9.12
9.12
7.2
6.5
6.5
5.3
6.5
5.3
5.3
4.8
6.1
6.1
4.9
5.8
5.8
5.2 4.72
5.2 4.72
C1, C2, C2L, I2, I2L
core speed grade
C3, I3, I3L
core speed grade
4.7 4.24 3.76
5.8 5.2 4.72
C1, C2, C2L, I2, I2L
core speed grade
FIFO
8.5
8.5
8.5
I3YY
core speed grade
10.3125 10.3125
7.84
7.84
7.04
9.76
9.76
7.92
7.2
4.7 4.24 3.76
4.7 4.24 3.76
4.2 3.84 3.44
5.7 4.88 4.56
5.7 4.88 4.56
4.5 3.96 3.6
5.7 4.88 4.56
4.5 3.96 3.6
4.5 3.96 3.6
4.1 3.52 3.28
3
C3, I3, I3L
core speed grade
8.5
8.5
8.5
8.2
7.2
C4, I4
core speed grade
6.56
9.12
9.12
7.2
C1, C2, C2L, I2, I2L
core speed grade
1
2
12.2
12.2
9.8
11.4
11.4
9.0
C1, C2, C2L, I2, I2L
core speed grade
C3, I3, I3L
core speed grade
C1, C2, C2L, I2, I2L
core speed grade
Register
10.3125 10.3125 10.3125 10.3125 6.1
I3YY
core speed grade
10.3125 10.3125
7.92
7.92
7.04
7.2
7.2
4.9
4.9
4.4
3
C3, I3, I3L
core speed grade
8.5
8.5
8.5
8.2
C4, I4
core speed grade
6.56
Notes to Table 25:
(1) The maximum data rate is in Gbps.
(2) The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency
can vary. In the register mode the pointers are fixed for low latency.
(3) The maximum data rate is also constrained by the transceiver speed grade. Refer to Table 1 for the transceiver speed grade.
Stratix V Device Datasheet
December 2015 Altera Corporation
INTEL [ INTEL ]
