Page 24
Switching Characteristics
(1)
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
(Part 7 of 7)
Transceiver Speed
Grade 1
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
(16)
tpll_lock
—
—
—
10
—
—
10
—
—
10
µs
Notes to Table 23:
(1) Speed grades shown in Table 23 refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the
Core/PCS speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination
offered. For more information about device ordering codes, refer to the Stratix V Device Overview.
(2) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.
(3) This supply must be connected to 1.0 V if the transceiver is configured at a data rate > 6.5 Gbps, and to 1.05 V if configured at a data rate >
10.3 Gbps when DFE is used. For data rates up to 6.5 Gbps, you can connect this supply to 0.85 V.
(4) This supply follows VCCR_GXB.
(5) The device cannot tolerate prolonged operation at this absolute maximum.
(6) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver
Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(7) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(8) The input reference clock frequency options depend on the data rate and the device speed grade.
(9) The line data rate may be limited by PCS-FPGA interface speed grade.
(10) Refer to Figure 1 for the GX channel AC gain curves. The total effective AC gain is the AC gain minus the DC gain.
(11) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
(12) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
(13) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is
functioning in the manual mode.
(14) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the
CDR is functioning in the manual mode.
(15) tpll_powerdown is the PLL powerdown minimum pulse width.
(16) tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset.
(17) To calculate the REFCLK rms phase jitter requirement for PCIe at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f(MHz) = REFCLK rms phase jitter at 100 MHz × 100/f.
(18) The maximum peak to peak differential input voltage VID after device configuration is equal to 4 × (absolute VMAX for receiver pin - VICM).
(19) For ES devices, RREF is 2000 1%.
(20) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f(MHz)
= REFCLK phase noise at 622 MHz + 20*log(f/622).
(21) SFP/+ optical modules require the host interface to have RD+/- differentially terminated with 100 . The internal OCT feature is available after
the Stratix V FPGA configuration is completed. Altera recommends that FPGA configuration is completed before inserting the optical module.
Otherwise, minimize unnecessary removal and insertion with unconfigured devices.
(22) Refer to Figure 1.
(23) For oversampling designs to support data rates less than the minimum specification, the CDR needs to be in LTR mode only.
(24) I3YY devices can achieve data rates up to 10.3125 Gbps.
(25) When you use fPLL as a TXPLL of the transceiver.
(26) REFCLKperformance requires to meet transmitter REFCLKphase noise specification.
(27) Minimum eye opening of 85 mV is only for the unstressed input eye condition.
Stratix V Device Datasheet
December 2015 Altera Corporation
INTEL [ INTEL ]
