Page 28
Switching Characteristics
Table 25. PLL Specifications for Cyclone V Devices (Part 2 of 3)
Symbol
Parameter
PLL closed-loop low bandwidth
Min
—
—
—
—
10
—
—
Typ
0.3
1.5
4
Max
—
Unit
MHz
MHz
fCLBW
PLL closed-loop medium bandwidth
—
(8)
PLL closed-loop high bandwidth
—
MHz
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
—
—
—
—
50
ps
Minimum pulse width on the areset signal
Input clock cycle-to-cycle jitter (FREF ≥ 100 MHz)
Input clock cycle-to-cycle jitter (FREF < 100 MHz)
—
ns
0.15
750
UI (p-p)
ps (p-p)
(4), (5)
tINCCJ
Period jitter for dedicated clock output in integer PLL
(FOUT ≥ 100 MHz)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
ps (p-p)
mUI (p-p)
ps (p-p)
(6)
tOUTPJ_DC
Period jitter for dedicated clock output in integer PLL
(FOUT < 100 MHz)
30
Period jitter for dedicated clock output in fractional PLL
(FOUT ≥ 100 MHz)
425 (10)
,
300 (11)
(6)
tFOUTPJ_DC
tOUTCCJ_DC
tFOUTCCJ_DC
Period jitter for dedicated clock output in fractional PLL
(FOUT < 100 MHz)
42.5 (10)
,
mUI (p-p)
ps (p-p)
30 (11)
Cycle-to-cycle jitter for dedicated clock output in integer PLL
(FOUT ≥ 100 MHz)
300
30
(6)
Cycle-to-cycle jitter for dedicated clock output in integer PLL
(FOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for dedicated clock output in fractional
PLL (FOUT ≥ 100 MHz)
425 (10)
300 (11)
,
(6)
Cycle-to-cycle jitter for dedicated clock output in fractional
PLL (FOUT < 100 MHz)
42.5 (10)
,
mUI (p-p)
ps (p-p)
30 (11)
Period jitter for clock output on a regular I/O in integer PLL
(FOUT ≥ 100 MHz)
650
65
(6), (9)
(6), (9),
tOUTPJ_IO
Period jitter for clock output on a regular I/O in integer PLL
(FOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Period jitter for clock output on a regular I/O in fractional PLL
(FOUT ≥ 100 MHz)
650
65
tFOUTPJ_IO
(10)
Period jitter for clock output on a regular I/O in fractional PLL
(FOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for clock output on regular I/O in integer
PLL (FOUT ≥ 100 MHz)
650
65
(6), (9)
tOUTCCJ_IO
Cycle-to-cycle jitter for clock output on regular I/O in integer
PLL (FOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for clock output on regular I/O in
fractional PLL (FOUT ≥ 100 MHz)
650
65
(6),
tFOUTCCJ_IO
(9), (10)
Cycle-to-cycle jitter for clock output on regular I/O in
fractional PLL (FOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Period jitter for dedicated clock output in cascaded PLLs (FOUT
≥ 100 MHz)
300
30
tCASC_OUTPJ_DC
(6), (7)
Period jitter for dedicated clock output in cascaded PLLs (FOUT
< 100 MHz)
mUI (p-p)
Cyclone V Device Datasheet
July 2014 Altera Corporation
INTEL [ INTEL ]
