Switching Characteristics
Page 27
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), and memory block specifications.
Clock Tree Specifications
Table 24 lists the clock tree specifications for Cyclone V devices.
Table 24. Clock Tree Performance for Cyclone V Devices
Performance
Parameter
–C6
Unit
–C7, –I7
550
–C8, –A7
460
Global clock and Regional clock
Peripheral clock
550
155
MHz
MHz
155
155
PLL Specifications
Table 25 lists the Cyclone V PLL block specifications. Cyclone V PLL block does not
include HPS PLL.
Table 25. PLL Specifications for Cyclone V Devices (Part 1 of 3)
Symbol Parameter
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
—
—
Max
670 (1)
622 (1)
500 (1)
325
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
–C6 speed grade
fIN
Input clock frequency
–C7, –I7 speed grades
–C8, –A7 speed grades
5
5
fINPFD
Integer input clock frequency to the PFD
Fractional input clock frequency to the PFD
5
fFINPFD
50
600
600
600
40
—
—
—
—
—
—
45
—
—
160
–C6 speed grade
1600
1400
1300
60
550 (3)
550 (3)
460 (3)
667 (3)
667 (3)
533 (3)
55
(2)
fVCO
PLL VCO operating range
–C7, –I7 speed grades
–C8, –A7 speed grades
tEINDUTY
Input clock or external feedback clock input duty cycle
–C6 speed grade
MHz
MHz
MHz
MHz
MHz
MHz
%
Output frequency for internal global
or regional clock
fOUT
–C7, –I7 speed grades
–C8, –A7 speed grades
–C6 speed grade
Output frequency for external clock
output
fOUT_EXT
–C7, –I7 speed grades
–C8, –A7 speed grades
tOUTDUTY
tFCOMP
Duty cycle for external clock output (when set to 50%)
External feedback clock compensation time
10
ns
tDYCONFIGCLK
Dynamic configuration clock for mgmt_clk and scanclk
100
MHz
Time required to lock from end-of-device configuration or
deassertion of areset
tLOCK
—
—
—
—
1
1
ms
ms
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
tDLOCK
July 2014 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
